mirror of
https://github.com/RPCS3/llvm-mirror.git
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5b6f2d0cd7
Uses a Custom implementation because the slot sizes being a multiple of the pointer size isn't really universal, even for the architectures that do have a simple "void *" va_list. llvm-svn: 295255
598 lines
21 KiB
C++
598 lines
21 KiB
C++
//===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file implements the LegalizerHelper class to legalize
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/// individual instructions and the LegalizeMachineIR wrapper pass for the
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/// primary legalization.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <sstream>
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#define DEBUG_TYPE "legalize-mir"
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using namespace llvm;
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LegalizerHelper::LegalizerHelper(MachineFunction &MF)
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: MRI(MF.getRegInfo()) {
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MIRBuilder.setMF(MF);
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::legalizeInstrStep(MachineInstr &MI,
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const LegalizerInfo &LegalizerInfo) {
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auto Action = LegalizerInfo.getAction(MI, MRI);
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switch (std::get<0>(Action)) {
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case LegalizerInfo::Legal:
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return AlreadyLegal;
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case LegalizerInfo::Libcall:
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return libcall(MI);
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case LegalizerInfo::NarrowScalar:
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return narrowScalar(MI, std::get<1>(Action), std::get<2>(Action));
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case LegalizerInfo::WidenScalar:
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return widenScalar(MI, std::get<1>(Action), std::get<2>(Action));
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case LegalizerInfo::Lower:
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return lower(MI, std::get<1>(Action), std::get<2>(Action));
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case LegalizerInfo::FewerElements:
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return fewerElementsVector(MI, std::get<1>(Action), std::get<2>(Action));
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case LegalizerInfo::Custom:
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return LegalizerInfo.legalizeCustom(MI, MRI, MIRBuilder) ? Legalized
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: UnableToLegalize;
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default:
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return UnableToLegalize;
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}
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::legalizeInstr(MachineInstr &MI,
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const LegalizerInfo &LegalizerInfo) {
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SmallVector<MachineInstr *, 4> WorkList;
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MIRBuilder.recordInsertions(
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[&](MachineInstr *MI) { WorkList.push_back(MI); });
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WorkList.push_back(&MI);
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bool Changed = false;
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LegalizeResult Res;
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unsigned Idx = 0;
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do {
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Res = legalizeInstrStep(*WorkList[Idx], LegalizerInfo);
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if (Res == UnableToLegalize) {
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MIRBuilder.stopRecordingInsertions();
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return UnableToLegalize;
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}
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Changed |= Res == Legalized;
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++Idx;
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} while (Idx < WorkList.size());
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MIRBuilder.stopRecordingInsertions();
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return Changed ? Legalized : AlreadyLegal;
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}
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void LegalizerHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
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SmallVectorImpl<unsigned> &VRegs) {
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unsigned Size = Ty.getSizeInBits();
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SmallVector<uint64_t, 4> Indexes;
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for (int i = 0; i < NumParts; ++i) {
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VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
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Indexes.push_back(i * Size);
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}
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MIRBuilder.buildExtract(VRegs, Indexes, Reg);
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}
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static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
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switch (Opcode) {
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case TargetOpcode::G_FREM:
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return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
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case TargetOpcode::G_FPOW:
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return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
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}
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llvm_unreachable("Unknown libcall function");
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::libcall(MachineInstr &MI) {
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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unsigned Size = Ty.getSizeInBits();
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MIRBuilder.setInstr(MI);
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switch (MI.getOpcode()) {
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default:
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return UnableToLegalize;
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case TargetOpcode::G_FPOW:
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case TargetOpcode::G_FREM: {
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auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
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Type *Ty = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
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auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
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auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
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const char *Name = TLI.getLibcallName(getRTLibDesc(MI.getOpcode(), Size));
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CLI.lowerCall(
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MIRBuilder, MachineOperand::CreateES(Name),
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{MI.getOperand(0).getReg(), Ty},
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{{MI.getOperand(1).getReg(), Ty}, {MI.getOperand(2).getReg(), Ty}});
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MI.eraseFromParent();
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return Legalized;
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}
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}
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}
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void LegalizerHelper::findInsertionsForRange(
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int64_t DstStart, int64_t DstEnd, MachineInstr::mop_iterator &CurOp,
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MachineInstr::mop_iterator &EndOp, MachineInstr &MI) {
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while (CurOp != MI.operands_end() && std::next(CurOp)->getImm() < DstStart)
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CurOp += 2;
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EndOp = CurOp;
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while (EndOp != MI.operands_end() && std::next(EndOp)->getImm() < DstEnd)
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EndOp += 2;
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}
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LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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unsigned TypeIdx,
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LLT NarrowTy) {
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// FIXME: Don't know how to handle secondary types yet.
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if (TypeIdx != 0)
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return UnableToLegalize;
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MIRBuilder.setInstr(MI);
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switch (MI.getOpcode()) {
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default:
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return UnableToLegalize;
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case TargetOpcode::G_ADD: {
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// Expand in terms of carry-setting/consuming G_ADDE instructions.
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unsigned NarrowSize = NarrowTy.getSizeInBits();
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int NumParts = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() /
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NarrowTy.getSizeInBits();
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SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
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SmallVector<uint64_t, 2> Indexes;
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extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
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extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
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unsigned CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
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MIRBuilder.buildConstant(CarryIn, 0);
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for (int i = 0; i < NumParts; ++i) {
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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unsigned CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
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MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
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Src2Regs[i], CarryIn);
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DstRegs.push_back(DstReg);
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Indexes.push_back(i * NarrowSize);
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CarryIn = CarryOut;
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}
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unsigned DstReg = MI.getOperand(0).getReg();
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MIRBuilder.buildSequence(DstReg, DstRegs, Indexes);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_INSERT: {
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if (TypeIdx != 0)
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return UnableToLegalize;
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unsigned NarrowSize = NarrowTy.getSizeInBits();
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int NumParts =
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MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
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SmallVector<unsigned, 2> SrcRegs, DstRegs;
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SmallVector<uint64_t, 2> Indexes;
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extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
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MachineInstr::mop_iterator CurOp = MI.operands_begin() + 2, EndOp;
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for (int i = 0; i < NumParts; ++i) {
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unsigned DstStart = i * NarrowSize;
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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Indexes.push_back(DstStart);
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findInsertionsForRange(DstStart, DstStart + NarrowSize, CurOp, EndOp, MI);
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if (CurOp == EndOp) {
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// No part of the insert affects this subregister, forward the original.
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DstRegs.push_back(SrcRegs[i]);
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continue;
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} else if (MRI.getType(CurOp->getReg()) == NarrowTy &&
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std::next(CurOp)->getImm() == DstStart) {
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// The entire subregister is defined by this insert, forward the new
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// value.
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DstRegs.push_back(CurOp->getReg());
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continue;
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}
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auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_INSERT)
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.addDef(DstReg)
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.addUse(SrcRegs[i]);
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for (; CurOp != EndOp; CurOp += 2) {
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unsigned Reg = CurOp->getReg();
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uint64_t Offset = std::next(CurOp)->getImm() - DstStart;
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// Make sure we don't have a cross-register insert.
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if (Offset + MRI.getType(Reg).getSizeInBits() > NarrowSize) {
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// FIXME: we should handle this case, though it's unlikely to be
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// common given ABI-related layout restrictions.
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return UnableToLegalize;
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}
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MIB.addUse(Reg);
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MIB.addImm(Offset);
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}
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DstRegs.push_back(DstReg);
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}
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assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
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MIRBuilder.buildSequence(MI.getOperand(0).getReg(), DstRegs, Indexes);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_LOAD: {
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unsigned NarrowSize = NarrowTy.getSizeInBits();
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int NumParts =
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MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
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LLT NarrowPtrTy = LLT::pointer(
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MRI.getType(MI.getOperand(1).getReg()).getAddressSpace(), NarrowSize);
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SmallVector<unsigned, 2> DstRegs;
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SmallVector<uint64_t, 2> Indexes;
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for (int i = 0; i < NumParts; ++i) {
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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unsigned SrcReg = MRI.createGenericVirtualRegister(NarrowPtrTy);
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unsigned Offset = MRI.createGenericVirtualRegister(LLT::scalar(64));
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MIRBuilder.buildConstant(Offset, i * NarrowSize / 8);
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MIRBuilder.buildGEP(SrcReg, MI.getOperand(1).getReg(), Offset);
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// TODO: This is conservatively correct, but we probably want to split the
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// memory operands in the future.
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MIRBuilder.buildLoad(DstReg, SrcReg, **MI.memoperands_begin());
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DstRegs.push_back(DstReg);
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Indexes.push_back(i * NarrowSize);
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}
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unsigned DstReg = MI.getOperand(0).getReg();
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MIRBuilder.buildSequence(DstReg, DstRegs, Indexes);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_STORE: {
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unsigned NarrowSize = NarrowTy.getSizeInBits();
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int NumParts =
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MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
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LLT NarrowPtrTy = LLT::pointer(
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MRI.getType(MI.getOperand(1).getReg()).getAddressSpace(), NarrowSize);
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SmallVector<unsigned, 2> SrcRegs;
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extractParts(MI.getOperand(0).getReg(), NarrowTy, NumParts, SrcRegs);
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for (int i = 0; i < NumParts; ++i) {
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowPtrTy);
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unsigned Offset = MRI.createGenericVirtualRegister(LLT::scalar(64));
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MIRBuilder.buildConstant(Offset, i * NarrowSize / 8);
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MIRBuilder.buildGEP(DstReg, MI.getOperand(1).getReg(), Offset);
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// TODO: This is conservatively correct, but we probably want to split the
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// memory operands in the future.
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MIRBuilder.buildStore(SrcRegs[i], DstReg, **MI.memoperands_begin());
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}
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MI.eraseFromParent();
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return Legalized;
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}
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}
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
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MIRBuilder.setInstr(MI);
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switch (MI.getOpcode()) {
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default:
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return UnableToLegalize;
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case TargetOpcode::G_ADD:
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case TargetOpcode::G_AND:
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case TargetOpcode::G_MUL:
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case TargetOpcode::G_OR:
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case TargetOpcode::G_XOR:
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case TargetOpcode::G_SUB:
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case TargetOpcode::G_SHL: {
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// Perform operation at larger width (any extension is fine here, high bits
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// don't affect the result) and then truncate the result back to the
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// original type.
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unsigned Src1Ext = MRI.createGenericVirtualRegister(WideTy);
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unsigned Src2Ext = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildAnyExt(Src1Ext, MI.getOperand(1).getReg());
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MIRBuilder.buildAnyExt(Src2Ext, MI.getOperand(2).getReg());
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unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildInstr(MI.getOpcode())
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.addDef(DstExt)
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.addUse(Src1Ext)
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.addUse(Src2Ext);
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MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_SDIV:
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case TargetOpcode::G_UDIV:
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case TargetOpcode::G_ASHR:
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case TargetOpcode::G_LSHR: {
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unsigned ExtOp = MI.getOpcode() == TargetOpcode::G_SDIV ||
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MI.getOpcode() == TargetOpcode::G_ASHR
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? TargetOpcode::G_SEXT
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: TargetOpcode::G_ZEXT;
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unsigned LHSExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildInstr(ExtOp).addDef(LHSExt).addUse(
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MI.getOperand(1).getReg());
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unsigned RHSExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildInstr(ExtOp).addDef(RHSExt).addUse(
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MI.getOperand(2).getReg());
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unsigned ResExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildInstr(MI.getOpcode())
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.addDef(ResExt)
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.addUse(LHSExt)
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.addUse(RHSExt);
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MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), ResExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_SELECT: {
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if (TypeIdx != 0)
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return UnableToLegalize;
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// Perform operation at larger width (any extension is fine here, high bits
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// don't affect the result) and then truncate the result back to the
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// original type.
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unsigned Src1Ext = MRI.createGenericVirtualRegister(WideTy);
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unsigned Src2Ext = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildAnyExt(Src1Ext, MI.getOperand(2).getReg());
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MIRBuilder.buildAnyExt(Src2Ext, MI.getOperand(3).getReg());
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unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildInstr(TargetOpcode::G_SELECT)
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.addDef(DstExt)
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.addReg(MI.getOperand(1).getReg())
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.addUse(Src1Ext)
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.addUse(Src2Ext);
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MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_FPTOSI:
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case TargetOpcode::G_FPTOUI: {
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if (TypeIdx != 0)
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return UnableToLegalize;
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unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildInstr(MI.getOpcode())
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.addDef(DstExt)
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.addUse(MI.getOperand(1).getReg());
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MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_SITOFP:
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case TargetOpcode::G_UITOFP: {
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if (TypeIdx != 1)
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return UnableToLegalize;
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unsigned Src = MI.getOperand(1).getReg();
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unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
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if (MI.getOpcode() == TargetOpcode::G_SITOFP) {
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MIRBuilder.buildSExt(SrcExt, Src);
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} else {
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assert(MI.getOpcode() == TargetOpcode::G_UITOFP && "Unexpected conv op");
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MIRBuilder.buildZExt(SrcExt, Src);
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}
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MIRBuilder.buildInstr(MI.getOpcode())
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.addDef(MI.getOperand(0).getReg())
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.addUse(SrcExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_INSERT: {
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if (TypeIdx != 0)
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return UnableToLegalize;
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unsigned Src = MI.getOperand(1).getReg();
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unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildAnyExt(SrcExt, Src);
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unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
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auto MIB = MIRBuilder.buildInsert(DstExt, SrcExt, MI.getOperand(2).getReg(),
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MI.getOperand(3).getImm());
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for (unsigned OpNum = 4; OpNum < MI.getNumOperands(); OpNum += 2) {
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MIB.addReg(MI.getOperand(OpNum).getReg());
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MIB.addImm(MI.getOperand(OpNum + 1).getImm());
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}
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MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_LOAD: {
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assert(alignTo(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(), 8) ==
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WideTy.getSizeInBits() &&
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"illegal to increase number of bytes loaded");
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unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildLoad(DstExt, MI.getOperand(1).getReg(),
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**MI.memoperands_begin());
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MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_STORE: {
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assert(alignTo(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(), 8) ==
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WideTy.getSizeInBits() &&
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"illegal to increase number of bytes modified by a store");
|
|
|
|
unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildAnyExt(SrcExt, MI.getOperand(0).getReg());
|
|
MIRBuilder.buildStore(SrcExt, MI.getOperand(1).getReg(),
|
|
**MI.memoperands_begin());
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_CONSTANT: {
|
|
unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildConstant(DstExt, *MI.getOperand(1).getCImm());
|
|
MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_FCONSTANT: {
|
|
unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildFConstant(DstExt, *MI.getOperand(1).getFPImm());
|
|
MIRBuilder.buildFPTrunc(MI.getOperand(0).getReg(), DstExt);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_BRCOND: {
|
|
unsigned TstExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildAnyExt(TstExt, MI.getOperand(0).getReg());
|
|
MIRBuilder.buildBrCond(TstExt, *MI.getOperand(1).getMBB());
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_ICMP: {
|
|
assert(TypeIdx == 1 && "unable to legalize predicate");
|
|
bool IsSigned = CmpInst::isSigned(
|
|
static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()));
|
|
unsigned Op0Ext = MRI.createGenericVirtualRegister(WideTy);
|
|
unsigned Op1Ext = MRI.createGenericVirtualRegister(WideTy);
|
|
if (IsSigned) {
|
|
MIRBuilder.buildSExt(Op0Ext, MI.getOperand(2).getReg());
|
|
MIRBuilder.buildSExt(Op1Ext, MI.getOperand(3).getReg());
|
|
} else {
|
|
MIRBuilder.buildZExt(Op0Ext, MI.getOperand(2).getReg());
|
|
MIRBuilder.buildZExt(Op1Ext, MI.getOperand(3).getReg());
|
|
}
|
|
MIRBuilder.buildICmp(
|
|
static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
|
|
MI.getOperand(0).getReg(), Op0Ext, Op1Ext);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_GEP: {
|
|
assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
|
|
unsigned OffsetExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildSExt(OffsetExt, MI.getOperand(2).getReg());
|
|
MI.getOperand(2).setReg(OffsetExt);
|
|
return Legalized;
|
|
}
|
|
}
|
|
}
|
|
|
|
LegalizerHelper::LegalizeResult
|
|
LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
|
|
using namespace TargetOpcode;
|
|
MIRBuilder.setInstr(MI);
|
|
|
|
switch(MI.getOpcode()) {
|
|
default:
|
|
return UnableToLegalize;
|
|
case TargetOpcode::G_SREM:
|
|
case TargetOpcode::G_UREM: {
|
|
unsigned QuotReg = MRI.createGenericVirtualRegister(Ty);
|
|
MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
|
|
.addDef(QuotReg)
|
|
.addUse(MI.getOperand(1).getReg())
|
|
.addUse(MI.getOperand(2).getReg());
|
|
|
|
unsigned ProdReg = MRI.createGenericVirtualRegister(Ty);
|
|
MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
|
|
MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
|
|
ProdReg);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_SMULO:
|
|
case TargetOpcode::G_UMULO: {
|
|
// Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
|
|
// result.
|
|
unsigned Res = MI.getOperand(0).getReg();
|
|
unsigned Overflow = MI.getOperand(1).getReg();
|
|
unsigned LHS = MI.getOperand(2).getReg();
|
|
unsigned RHS = MI.getOperand(3).getReg();
|
|
|
|
MIRBuilder.buildMul(Res, LHS, RHS);
|
|
|
|
unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
|
|
? TargetOpcode::G_SMULH
|
|
: TargetOpcode::G_UMULH;
|
|
|
|
unsigned HiPart = MRI.createGenericVirtualRegister(Ty);
|
|
MIRBuilder.buildInstr(Opcode)
|
|
.addDef(HiPart)
|
|
.addUse(LHS)
|
|
.addUse(RHS);
|
|
|
|
unsigned Zero = MRI.createGenericVirtualRegister(Ty);
|
|
MIRBuilder.buildConstant(Zero, 0);
|
|
MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
}
|
|
}
|
|
|
|
LegalizerHelper::LegalizeResult
|
|
LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
|
|
LLT NarrowTy) {
|
|
// FIXME: Don't know how to handle secondary types yet.
|
|
if (TypeIdx != 0)
|
|
return UnableToLegalize;
|
|
switch (MI.getOpcode()) {
|
|
default:
|
|
return UnableToLegalize;
|
|
case TargetOpcode::G_ADD: {
|
|
unsigned NarrowSize = NarrowTy.getSizeInBits();
|
|
unsigned DstReg = MI.getOperand(0).getReg();
|
|
int NumParts = MRI.getType(DstReg).getSizeInBits() / NarrowSize;
|
|
|
|
MIRBuilder.setInstr(MI);
|
|
|
|
SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
|
|
SmallVector<uint64_t, 2> Indexes;
|
|
extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
|
|
extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
|
|
|
|
for (int i = 0; i < NumParts; ++i) {
|
|
unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
|
|
MIRBuilder.buildAdd(DstReg, Src1Regs[i], Src2Regs[i]);
|
|
DstRegs.push_back(DstReg);
|
|
Indexes.push_back(i * NarrowSize);
|
|
}
|
|
|
|
MIRBuilder.buildSequence(DstReg, DstRegs, Indexes);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
}
|
|
}
|