Tom Stellard 5aea8f0472 Revert "[RISCV] Fix reporting of incorrect commutable operand indices" ... This reverts commit a7933290f72a08dc060d38fa52772a9cc33ed9ba. This commit caused some bot failures: clang-with-thin-lto-ubuntu-release lld-x86_64-win-release llvm-clang-x86_64-expensive-checks-debian-release		2021-08-24 21:59:54 -07:00
..
AArch64	[AArch64] Fix comparison peephole opt with non-0/1 immediate (PR51476)	2021-08-18 20:07:23 -07:00
AMDGPU	AMDGPU/GlobalISel: Fix selecting G_SEXTLOAD/G_ZEXTLOAD pre-gfx9	2021-07-27 15:56:42 -04:00
ARC
ARM	[ARM][atomicrmw] Fix CMP_SWAP_32 expand assert	2021-08-18 12:14:24 -07:00
AVR	[AVR] Only support sp, r0 and r1 in llvm.read_register	2021-07-24 14:03:27 +02:00
BPF	BPF: avoid NE/EQ loop exit condition	2021-08-06 12:45:53 -07:00
Generic	[PowerPC] Add pwr7 and pwr10 support to IBM MASSV pass on AIX	2021-07-26 23:21:38 +00:00
Hexagon	[Hexagon] Fix resetting dead registers in DBG_VALUE_LISTs	2021-07-27 18:36:28 -05:00
Inputs
Lanai
M68k
Mips	[llvm][sve] Lowering for VLS truncating stores	2021-07-23 14:04:55 +01:00
MIR
MSP430
NVPTX	[NVPTX] Add select(cc,binop(),binop()) fast-math tests	2021-07-18 15:30:24 +01:00
PowerPC	[PowerPC] Disable CTR Loop generate for fma with the PPC double double type.	2021-08-17 20:22:13 -07:00
RISCV	Revert "[RISCV] Fix reporting of incorrect commutable operand indices"	2021-08-24 21:59:54 -07:00
SPARC
SystemZ	[SystemZ][z/OS] Initial code to generate assembly files on z/OS	2021-07-27 11:29:15 -04:00
Thumb
Thumb2	[ARM] Implement isLoad/StoreFromStackSlot for MVE stack stores accesses	2021-07-27 09:11:58 +01:00
VE
WebAssembly	[WebAssembly] Codegen for extmul SIMD instructions	2021-07-27 08:41:30 -07:00
WinCFGuard
WinEH
X86	[X86][AVX] Extract SUBV_BROADCAST constant bits from just the lower subvector range (PR51281)	2021-08-18 12:15:46 -07:00
XCore