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8ded1a7aa8
This patch fixes some issues with the RORB pseudo instruction.
- A minor issue in which the instructions were said to use the SREG,
which is not true.
- An issue with the BLD instruction, which did not have an output operand.
- A major issue in which invalid instructions were generated. The fix
also reduce RORB from 4 to 3 instructions, so it's also a small
optimization.
These issues were flagged by the machine verifier.
Differential Revision: https://reviews.llvm.org/D96957
59 lines
1.0 KiB
LLVM
59 lines
1.0 KiB
LLVM
; RUN: llc < %s -march=avr | FileCheck %s
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; Bit rotation tests.
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; CHECK-LABEL: rol8:
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define i8 @rol8(i8 %val, i8 %amt) {
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; CHECK: andi r22, 7
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; CHECK-NEXT: dec r22
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; CHECK-NEXT: brmi .LBB0_2
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; CHECK-NEXT: .LBB0_1:
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; CHECK-NEXT: lsl r24
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; CHECK-NEXT: adc r24, r1
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; CHECK-NEXT: dec r22
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; CHECK-NEXT: brpl .LBB0_1
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: ret
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%mod = urem i8 %amt, 8
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%inv = sub i8 8, %mod
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%parta = shl i8 %val, %mod
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%partb = lshr i8 %val, %inv
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%rotl = or i8 %parta, %partb
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ret i8 %rotl
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}
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; CHECK-LABEL: ror8:
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define i8 @ror8(i8 %val, i8 %amt) {
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; CHECK: andi r22, 7
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; CHECK-NEXT: dec r22
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; CHECK-NEXT: brmi .LBB1_2
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; CHECK-NEXT: .LBB1_1:
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; CHECK-NEXT: bst r24, 0
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; CHECK-NEXT: ror r24
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; CHECK-NEXT: bld r24, 7
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; CHECK-NEXT: dec r22
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; CHECK-NEXT: brpl .LBB1_1
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; CHECK-NEXT: .LBB1_2:
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; CHECK-NEXT: ret
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%mod = urem i8 %amt, 8
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%inv = sub i8 8, %mod
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%parta = lshr i8 %val, %mod
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%partb = shl i8 %val, %inv
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%rotr = or i8 %parta, %partb
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ret i8 %rotr
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}
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