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2d913ae276
Summary: This adds the unpredicated forms of six different MVE intrinsics which all round a vector of floating-point numbers to integer values, leaving them still in FP format, differing only in rounding mode and exception settings. Five of them map to existing target-independent intrinsics in LLVM IR, such as @llvm.trunc and @llvm.rint. The sixth, mapping to the `vrintn` instruction, is done by inventing a target-specific intrinsic. (`vrintn` behaves the same as `vrintx` in terms of the output value: the side effects on the FPSCR flags are the only difference between the two. But ACLE specifies separate user-callable intrinsics for the two, so the side effects matter enough to make sure we generate the right one of the two instructions in each case.) Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard Reviewed By: miyuki Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74333
26 lines
880 B
LLVM
26 lines
880 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
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define arm_aapcs_vfpcc <8 x half> @test_vrndnq_f16(<8 x half> %a) {
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; CHECK-LABEL: test_vrndnq_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vrintn.f16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = tail call <8 x half> @llvm.arm.mve.vrintn.v8f16(<8 x half> %a)
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ret <8 x half> %0
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}
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define arm_aapcs_vfpcc <4 x float> @test_vrndnq_f32(<4 x float> %a) {
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; CHECK-LABEL: test_vrndnq_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vrintn.f32 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = tail call <4 x float> @llvm.arm.mve.vrintn.v4f32(<4 x float> %a)
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ret <4 x float> %0
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}
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declare <8 x half> @llvm.arm.mve.vrintn.v8f16(<8 x half>)
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declare <4 x float> @llvm.arm.mve.vrintn.v4f32(<4 x float>)
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