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680d78da27
Support insert/extract_subreg intrinsic instructions for v512i1 registers and add regression tests. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D94298
33 lines
1.0 KiB
LLVM
33 lines
1.0 KiB
LLVM
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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;;; Test insert intrinsic instructions
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;;;
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;;; Note:
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;;; We test insert_vm512u and insert_vm512l pseudo instructions.
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; Function Attrs: nounwind readnone
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define fastcc <512 x i1> @insert_vm512u(<512 x i1> %0, <256 x i1> %1) {
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; CHECK-LABEL: insert_vm512u:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andm %vm2, %vm0, %vm4
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call <512 x i1> @llvm.ve.vl.insert.vm512u(<512 x i1> %0, <256 x i1> %1)
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ret <512 x i1> %3
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}
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; Function Attrs: nounwind readnone
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declare <512 x i1> @llvm.ve.vl.insert.vm512u(<512 x i1>, <256 x i1>)
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; Function Attrs: nounwind readnone
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define fastcc <512 x i1> @insert_vm512l(<512 x i1> %0, <256 x i1> %1) {
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; CHECK-LABEL: insert_vm512l:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andm %vm3, %vm0, %vm4
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call <512 x i1> @llvm.ve.vl.insert.vm512l(<512 x i1> %0, <256 x i1> %1)
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ret <512 x i1> %3
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}
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; Function Attrs: nounwind readnone
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declare <512 x i1> @llvm.ve.vl.insert.vm512l(<512 x i1>, <256 x i1>)
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