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https://github.com/RPCS3/llvm-mirror.git
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abc19cb49b
Change the way to truncate i64 to i32 in I64 registers. VE assumed sext values previously. Change it to zext values this time to make it match to the LLVM behaviour. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D92226
87 lines
2.9 KiB
LLVM
87 lines
2.9 KiB
LLVM
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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;;; Test prefetch vector intrinsic instructions
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;;;
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;;; Note:
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;;; We test LSVrr_v and LVSvr instructions.
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; Function Attrs: nounwind
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define void @lsv_vvss(i8* %0, i64 %1, i32 signext %2) {
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; CHECK-LABEL: lsv_vvss:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s3, 256
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; CHECK-NEXT: lvl %s3
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: and %s2, %s2, (32)0
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; CHECK-NEXT: lsv %v0(%s2), %s1
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; CHECK-NEXT: vst %v0, 8, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
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%5 = tail call fast <256 x double> @llvm.ve.vl.lsv.vvss(<256 x double> %4, i32 %2, i64 %1)
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tail call void @llvm.ve.vl.vst.vssl(<256 x double> %5, i64 8, i8* %0, i32 256)
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ret void
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}
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; Function Attrs: nounwind readonly
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declare <256 x double> @llvm.ve.vl.vld.vssl(i64, i8*, i32)
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.lsv.vvss(<256 x double>, i32, i64)
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; Function Attrs: nounwind writeonly
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declare void @llvm.ve.vl.vst.vssl(<256 x double>, i64, i8*, i32)
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; Function Attrs: nounwind readonly
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define i64 @lvsl_vssl_imm(i8* readonly %0, i32 signext %1) {
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; CHECK-LABEL: lvsl_vssl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s2, 256
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: and %s0, %s1, (32)0
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; CHECK-NEXT: lvs %s0, %v0(%s0)
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
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%4 = tail call i64 @llvm.ve.vl.lvsl.svs(<256 x double> %3, i32 %1)
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ret i64 %4
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.ve.vl.lvsl.svs(<256 x double>, i32)
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; Function Attrs: nounwind readonly
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define double @lvsd_vssl_imm(i8* readonly %0, i32 signext %1) {
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; CHECK-LABEL: lvsd_vssl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s2, 256
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: and %s0, %s1, (32)0
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; CHECK-NEXT: lvs %s0, %v0(%s0)
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
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%4 = tail call fast double @llvm.ve.vl.lvsd.svs(<256 x double> %3, i32 %1)
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ret double %4
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}
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; Function Attrs: nounwind readnone
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declare double @llvm.ve.vl.lvsd.svs(<256 x double>, i32)
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; Function Attrs: nounwind readonly
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define float @lvss_vssl_imm(i8* readonly %0, i32 signext %1) {
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; CHECK-LABEL: lvss_vssl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s2, 256
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: and %s0, %s1, (32)0
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; CHECK-NEXT: lvs %s0, %v0(%s0)
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
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%4 = tail call fast float @llvm.ve.vl.lvss.svs(<256 x double> %3, i32 %1)
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ret float %4
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}
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; Function Attrs: nounwind readnone
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declare float @llvm.ve.vl.lvss.svs(<256 x double>, i32)
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