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e3d737a117
Add vrmax, vrmin, vfrmax, vfrmin, vrand, vror, and vrxor intrinsic instructions and regression tests. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D92941
205 lines
7.1 KiB
LLVM
205 lines
7.1 KiB
LLVM
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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;;; Test vector minimum intrinsic instructions
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;;;
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;;; Note:
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;;; We test VRMIN*vl and VRMIN*vl_v instructions.
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vrminswfstsx_vvl(<256 x double> %0) {
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; CHECK-LABEL: vrminswfstsx_vvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vrmins.w.fst.sx %v0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vrminswfstsx.vvl(<256 x double> %0, i32 256)
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ret <256 x double> %2
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vrminswfstsx.vvl(<256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vrminswfstsx_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vrminswfstsx_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vrmins.w.fst.sx %v1, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vrminswfstsx.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vrminswfstsx.vvvl(<256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vrminswlstsx_vvl(<256 x double> %0) {
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; CHECK-LABEL: vrminswlstsx_vvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vrmins.w.lst.sx %v0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vrminswlstsx.vvl(<256 x double> %0, i32 256)
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ret <256 x double> %2
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vrminswlstsx.vvl(<256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vrminswlstsx_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vrminswlstsx_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vrmins.w.lst.sx %v1, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vrminswlstsx.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vrminswlstsx.vvvl(<256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vrminswfstzx_vvl(<256 x double> %0) {
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; CHECK-LABEL: vrminswfstzx_vvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vrmins.w.fst.zx %v0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vrminswfstzx.vvl(<256 x double> %0, i32 256)
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ret <256 x double> %2
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vrminswfstzx.vvl(<256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vrminswfstzx_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vrminswfstzx_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vrmins.w.fst.zx %v1, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vrminswfstzx.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vrminswfstzx.vvvl(<256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vrminswlstzx_vvl(<256 x double> %0) {
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; CHECK-LABEL: vrminswlstzx_vvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vrmins.w.lst.zx %v0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vrminswlstzx.vvl(<256 x double> %0, i32 256)
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ret <256 x double> %2
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vrminswlstzx.vvl(<256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vrminswlstzx_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vrminswlstzx_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vrmins.w.lst.zx %v1, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vrminswlstzx.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vrminswlstzx.vvvl(<256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vrminslfst_vvl(<256 x double> %0) {
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; CHECK-LABEL: vrminslfst_vvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vrmins.l.fst %v0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vrminslfst.vvl(<256 x double> %0, i32 256)
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ret <256 x double> %2
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vrminslfst.vvl(<256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vrminslfst_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vrminslfst_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vrmins.l.fst %v1, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vrminslfst.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vrminslfst.vvvl(<256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vrminsllst_vvl(<256 x double> %0) {
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; CHECK-LABEL: vrminsllst_vvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vrmins.l.lst %v0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vrminsllst.vvl(<256 x double> %0, i32 256)
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ret <256 x double> %2
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vrminsllst.vvl(<256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vrminsllst_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vrminsllst_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vrmins.l.lst %v1, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vrminsllst.vvvl(<256 x double> %0, <256 x double> %1, i32 128)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vrminsllst.vvvl(<256 x double>, <256 x double>, i32)
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