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e3d737a117
Add vrmax, vrmin, vfrmax, vfrmin, vrand, vror, and vrxor intrinsic instructions and regression tests. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D92941
37 lines
1.2 KiB
LLVM
37 lines
1.2 KiB
LLVM
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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;;; Test vector reduction exclusive or intrinsic instructions
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;;;
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;;; Note:
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;;; We test VRXOR*vl and VRXOR*vml instructions.
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vrxor_vvl(<256 x double> %0) {
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; CHECK-LABEL: vrxor_vvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vrxor %v0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vrxor.vvl(<256 x double> %0, i32 256)
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ret <256 x double> %2
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vrxor.vvl(<256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vrxor_vvml(<256 x double> %0, <256 x i1> %1) {
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; CHECK-LABEL: vrxor_vvml:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vrxor %v0, %v0, %vm1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vrxor.vvml(<256 x double> %0, <256 x i1> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vrxor.vvml(<256 x double>, <256 x i1>, i32)
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