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LLVM test CodeGen/AArch64/aarch64-tbz.ll tries to check for the absence of a sequence of instructions with several CHECK-NOT with one of those directives using a variable defined in another. However CHECK-NOT are checked independently so that is using a variable defined in a pattern that should not occur in the input. This commit removes the definition and uses of variable to check each line independently, making the check stronger than the current one. It also removes unnecessary regex match for labels. Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D99602
100 lines
2.9 KiB
LLVM
100 lines
2.9 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnueabi < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnueabi -cgp-verify-bfi-updates=true < %s | FileCheck %s
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; CHECK-LABEL: test1
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; CHECK: tbz {{w[0-9]}}, #3, {{.LBB0_3}}
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; CHECK: tbz w[[REG1:[0-9]+]], #2, {{.LBB0_3}}
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; CHECK-NOT: and x{{[0-9]+}}, x[[REG1]], #0x4
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; CHECK-NOT: cbz x{{[0-9]+}}, .LBB0_3
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; CHECK: b
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define void @test1(i64 %A, i64 %B) {
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entry:
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%and = and i64 %A, 4
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%notlhs = icmp eq i64 %and, 0
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%and.1 = and i64 %B, 8
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%0 = icmp eq i64 %and.1, 0
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%1 = or i1 %0, %notlhs
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br i1 %1, label %if.end3, label %if.then2
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if.then2: ; preds = %entry
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tail call void @foo(i64 %A, i64 %B)
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br label %if.end3
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if.end3: ; preds = %if.then2, %entry
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ret void
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}
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; CHECK-LABEL: test2
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; CHECK: cbz {{x[0-9]}}, {{.LBB1_3}}
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; CHECK: tbz w[[REG1:[0-9]+]], #3, {{.LBB1_3}}
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; CHECK-NOT: and x{{[0-9]+}}, x[[REG1]], #0x08
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; CHECK-NOT: cbz x{{[0-9]+}}, .LBB1_3
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define void @test2(i64 %A, i64* readonly %B) #0 {
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entry:
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%tobool = icmp eq i64* %B, null
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%and = and i64 %A, 8
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%tobool1 = icmp eq i64 %and, 0
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%or.cond = or i1 %tobool, %tobool1
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br i1 %or.cond, label %if.end3, label %if.then2
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if.then2: ; preds = %entry
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%0 = load i64, i64* %B, align 4
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tail call void @foo(i64 %A, i64 %0)
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br label %if.end3
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if.end3: ; preds = %entry, %if.then2
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ret void
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}
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; Make sure we use the W variant when log2(mask) is < 32.
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; CHECK-LABEL: test3
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; CHECK: tbz {{w[0-9]}}, #3, {{.LBB2_3}}
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; CHECK: tbz w[[REG1:[0-9]+]], #28, {{.LBB2_3}}
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; CHECK-NOT: and x{{[0-9]+}}, x[[REG1]]
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; CHECK-NOT: cbz x{{[0-9]+}}, .LBB2_3
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define void @test3(i64 %A, i64 %B) {
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entry:
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%shift = shl i64 1, 28
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%and = and i64 %A, %shift
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%notlhs = icmp eq i64 %and, 0
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%and.1 = and i64 %B, 8
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%0 = icmp eq i64 %and.1, 0
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%1 = or i1 %0, %notlhs
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br i1 %1, label %if.then2, label %if.end3
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if.then2: ; preds = %entry
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tail call void @foo(i64 %A, i64 %B)
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br label %if.end3
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if.end3: ; preds = %if.then2, %entry
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ret void
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}
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; CHECK-LABEL: test4
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; CHECK: tbz {{w[0-9]}}, #3, {{.LBB3_3}}
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; CHECK: tbz [[REG1:x[0-9]+]], #35, {{.LBB3_3}}
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; CHECK-NOT: and x{{[0-9]+}}, x[[REG1]]
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; CHECK-NOT: cbz x{{[0-9]+}}, .LBB2_3
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define void @test4(i64 %A, i64 %B) {
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entry:
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%shift = shl i64 1, 35
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%and = and i64 %A, %shift
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%notlhs = icmp eq i64 %and, 0
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%and.1 = and i64 %B, 8
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%0 = icmp eq i64 %and.1, 0
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%1 = or i1 %0, %notlhs
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br i1 %1, label %if.then2, label %if.end3
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if.then2: ; preds = %entry
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tail call void @foo(i64 %A, i64 %B)
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br label %if.end3
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if.end3: ; preds = %if.then2, %entry
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ret void
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}
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declare void @foo(i64, i64)
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