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llvm-mirror/test/CodeGen/AArch64/arm64_32-memcpy.ll
Tim Northover 1bb14916f2 AArch64: support arm64_32, an ILP32 slice for watchOS.
This is the main CodeGen patch to support the arm64_32 watchOS ABI in LLVM.
FastISel is mostly disabled for now since it would generate incorrect code for
ILP32.

llvm-svn: 371722
2019-09-12 10:22:23 +00:00

67 lines
1.7 KiB
LLVM

; RUN: llc -mtriple=arm64_32-apple-ios9.0 -o - %s | FileCheck %s
define i64 @test_memcpy(i64* %addr, i8* %src, i1 %tst) minsize {
; CHECK-LABEL: test_memcpy:
; CHECK: ldr [[VAL64:x[0-9]+]], [x0]
; [...]
; CHECK: and x0, [[VAL64]], #0xffffffff
; CHECK: bl _memcpy
%val64 = load i64, i64* %addr
br i1 %tst, label %true, label %false
true:
ret i64 %val64
false:
%val32 = trunc i64 %val64 to i32
%val.ptr = inttoptr i32 %val32 to i8*
call void @llvm.memcpy.p0i8.p0i8.i32(i8* %val.ptr, i8* %src, i32 128, i32 0, i1 1)
ret i64 undef
}
define i64 @test_memmove(i64* %addr, i8* %src, i1 %tst) minsize {
; CHECK-LABEL: test_memmove:
; CHECK: ldr [[VAL64:x[0-9]+]], [x0]
; [...]
; CHECK: and x0, [[VAL64]], #0xffffffff
; CHECK: bl _memmove
%val64 = load i64, i64* %addr
br i1 %tst, label %true, label %false
true:
ret i64 %val64
false:
%val32 = trunc i64 %val64 to i32
%val.ptr = inttoptr i32 %val32 to i8*
call void @llvm.memmove.p0i8.p0i8.i32(i8* %val.ptr, i8* %src, i32 128, i32 0, i1 1)
ret i64 undef
}
define i64 @test_memset(i64* %addr, i8* %src, i1 %tst) minsize {
; CHECK-LABEL: test_memset:
; CHECK: ldr [[VAL64:x[0-9]+]], [x0]
; [...]
; CHECK: and x0, [[VAL64]], #0xffffffff
; CHECK: bl _memset
%val64 = load i64, i64* %addr
br i1 %tst, label %true, label %false
true:
ret i64 %val64
false:
%val32 = trunc i64 %val64 to i32
%val.ptr = inttoptr i32 %val32 to i8*
call void @llvm.memset.p0i8.i32(i8* %val.ptr, i8 42, i32 256, i32 0, i1 1)
ret i64 undef
}
declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
declare void @llvm.memmove.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
declare void @llvm.memset.p0i8.i32(i8*, i8, i32, i32, i1)