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9a270624d8
Custom-expand legal VECREDUCE_FADD SDNodes to benefit from pair-wise faddp instructions. Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D59259
102 lines
3.7 KiB
LLVM
102 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
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declare half @llvm.vector.reduce.fadd.f16.v1f16(half, <1 x half>)
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declare float @llvm.vector.reduce.fadd.f32.v1f32(float, <1 x float>)
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declare double @llvm.vector.reduce.fadd.f64.v1f64(double, <1 x double>)
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declare fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128, <1 x fp128>)
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declare float @llvm.vector.reduce.fadd.f32.v3f32(float, <3 x float>)
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declare float @llvm.vector.reduce.fadd.f32.v5f32(float, <5 x float>)
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declare fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128, <2 x fp128>)
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declare float @llvm.vector.reduce.fadd.f32.v16f32(float, <16 x float>)
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define half @test_v1f16(<1 x half> %a) nounwind {
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; CHECK-LABEL: test_v1f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call reassoc half @llvm.vector.reduce.fadd.f16.v1f16(half -0.0, <1 x half> %a)
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ret half %b
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}
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define float @test_v1f32(<1 x float> %a) nounwind {
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; CHECK-LABEL: test_v1f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
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; CHECK-NEXT: ret
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%b = call reassoc float @llvm.vector.reduce.fadd.f32.v1f32(float -0.0, <1 x float> %a)
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ret float %b
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}
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define double @test_v1f64(<1 x double> %a) nounwind {
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; CHECK-LABEL: test_v1f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call reassoc double @llvm.vector.reduce.fadd.f64.v1f64(double -0.0, <1 x double> %a)
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ret double %b
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}
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define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v1f128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call reassoc fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128 0xL00000000000000008000000000000000, <1 x fp128> %a)
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ret fp128 %b
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}
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define float @test_v3f32(<3 x float> %a) nounwind {
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; CHECK-LABEL: test_v3f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-2147483648
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; CHECK-NEXT: fmov s1, w8
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; CHECK-NEXT: mov v0.s[3], v1.s[0]
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; CHECK-NEXT: faddp v0.4s, v0.4s, v0.4s
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; CHECK-NEXT: faddp s0, v0.2s
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; CHECK-NEXT: ret
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%b = call reassoc float @llvm.vector.reduce.fadd.f32.v3f32(float -0.0, <3 x float> %a)
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ret float %b
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}
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define float @test_v5f32(<5 x float> %a) nounwind {
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; CHECK-LABEL: test_v5f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
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; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
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; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
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; CHECK-NEXT: movi v5.4s, #128, lsl #24
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; CHECK-NEXT: mov v0.s[1], v1.s[0]
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; CHECK-NEXT: mov v0.s[2], v2.s[0]
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; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4
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; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3
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; CHECK-NEXT: mov v0.s[3], v3.s[0]
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; CHECK-NEXT: mov v5.s[0], v4.s[0]
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; CHECK-NEXT: fadd v0.4s, v0.4s, v5.4s
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; CHECK-NEXT: faddp v0.4s, v0.4s, v0.4s
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; CHECK-NEXT: faddp s0, v0.2s
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; CHECK-NEXT: ret
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%b = call reassoc float @llvm.vector.reduce.fadd.f32.v5f32(float -0.0, <5 x float> %a)
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ret float %b
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}
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define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v2f128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: b __addtf3
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%b = call reassoc fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 0xL00000000000000008000000000000000, <2 x fp128> %a)
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ret fp128 %b
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}
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define float @test_v16f32(<16 x float> %a) nounwind {
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; CHECK-LABEL: test_v16f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fadd v1.4s, v1.4s, v3.4s
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; CHECK-NEXT: fadd v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: fadd v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: faddp v0.4s, v0.4s, v0.4s
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; CHECK-NEXT: faddp s0, v0.2s
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; CHECK-NEXT: ret
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%b = call reassoc float @llvm.vector.reduce.fadd.f32.v16f32(float -0.0, <16 x float> %a)
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ret float %b
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}
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