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Summary: computeKnownBitsForTargetNode was not defined for Lanai which resulted in additional AND's with 0x1 for the output of SETCC instructions. Reviewers: eliben, majnemer Reviewed By: majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29605 llvm-svn: 302568
49 lines
1.4 KiB
LLVM
49 lines
1.4 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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; Test that unnecessary masking with 0x1 is not inserted.
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target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
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target triple = "lanai"
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; CHECK-LABEL: masking:
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; CHECK-NOT: mov 1
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define i32 @masking(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
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entry:
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%cmp = icmp ne i32 %a, 0
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%cmp1 = icmp ult i32 %a, %b
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%or.cond = and i1 %cmp, %cmp1
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br i1 %or.cond, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp2 = icmp ne i32 %b, 0
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%cmp4 = icmp ult i32 %b, %c
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%or.cond29 = and i1 %cmp2, %cmp4
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br i1 %or.cond29, label %return, label %if.end6
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if.end6: ; preds = %if.end
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%cmp7 = icmp ne i32 %c, 0
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%cmp9 = icmp ult i32 %c, %d
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%or.cond30 = and i1 %cmp7, %cmp9
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br i1 %or.cond30, label %return, label %if.end11
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if.end11: ; preds = %if.end6
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%cmp12 = icmp ne i32 %d, 0
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%cmp14 = icmp ult i32 %d, %a
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%or.cond31 = and i1 %cmp12, %cmp14
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%b. = select i1 %or.cond31, i32 %b, i32 21
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ret i32 %b.
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return: ; preds = %if.end6, %if.end, %entry
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%retval.0 = phi i32 [ %c, %entry ], [ %d, %if.end ], [ %a, %if.end6 ]
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ret i32 %retval.0
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}
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; CHECK-LABEL: notnot:
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; CHECK-NOT: mov 1
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define i32 @notnot(i32 %x) {
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entry:
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%tobool = icmp ne i32 %x, 0
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%lnot.ext = zext i1 %tobool to i32
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ret i32 %lnot.ext
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}
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