Sander de Smalen 7c485019b2 [AArch64][SVE] Asm: Support for structured LD3 (scalar+imm) load instructions. ... Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45623 llvm-svn: 330116		2018-04-16 10:10:48 +00:00
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AArch64	[AArch64][SVE] Asm: Support for structured LD3 (scalar+imm) load instructions.	2018-04-16 10:10:48 +00:00
AMDGPU	[AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32	2018-04-11 13:13:30 +00:00
ARM	[ARM] Do not convert some vmov instructions	2018-04-04 08:54:19 +00:00
AsmParser	Use .set instead of = when printing assignment in assembly output	2018-03-27 16:44:41 +00:00
AVR
BPF	bpf: New disassembler testcases for 32-bit subregister support	2018-02-23 23:49:35 +00:00
COFF	[IR] Avoid the need to prefix MS C++ symbols with '\01'	2018-03-16 20:13:32 +00:00
Disassembler	[X86] Add the bizarro movsww and movzww mnemonics for the disassembler.	2018-04-13 23:57:54 +00:00
ELF	[DWARFv5] Fuss with asm syntax for conveying MD5 checksum.	2018-04-11 15:14:05 +00:00
Hexagon	[Hexagon] Recognize and handle :endloop01	2018-03-30 15:29:47 +00:00
Lanai
MachO	MachO: trap unreachable instructions	2018-04-13 22:25:20 +00:00
Mips	[mips] Restrict certain trap instructions for micromipsr6	2018-04-16 09:22:20 +00:00
PowerPC	[PowerPC] Code cleanup. Remove instructions that were withdrawn from Power 9.	2018-02-23 15:55:16 +00:00
RISCV	[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0	2018-04-12 19:22:40 +00:00
Sparc
SystemZ
WebAssembly	[WebAssembly] libObject: Don't include the name the size of custom sections	2018-04-12 20:31:12 +00:00
X86	[X86] Introduce cldemote instruction	2018-04-13 07:35:08 +00:00