Craig Topper 0441629838 [X86] Add the bizarro movsww and movzww mnemonics for the disassembler. ... The destination size of the movzx/movsx instruction is controlled by the normal operand size mechanisms. Only the input type is fixed. This means that a 0x66 prefix on the encoding for zext/sext 16->32 should really produce a 16->16 instruction. Functionally this is equivalent to a GR16->GR16 move since bits 16 and above will be preserved. So nothing is actually extended. llvm-svn: 330078		2018-04-13 23:57:54 +00:00
..
AArch64	[AArch64] Fix spelling of ICH_ELRSR_EL2 system register	2018-02-06 09:39:04 +00:00
AMDGPU	[AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32	2018-04-11 13:13:30 +00:00
ARC	[ARC] Add LImm support for J/JL	2018-04-13 15:10:34 +00:00
ARM	[ARM]Decoding MSR with unpredictable destination register causes an assert	2018-03-06 15:21:19 +00:00
Hexagon	[Hexagon] Remove trailing spaces, NFC	2017-11-22 20:43:00 +00:00
Lanai
Mips	[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx.	2018-04-12 12:37:02 +00:00
PowerPC	[PowerPC] Code cleanup. Remove instructions that were withdrawn from Power 9.	2018-02-23 15:55:16 +00:00
Sparc
SystemZ	[SystemZ] Add support for IBM z14 processor (3/3)	2017-07-17 17:44:20 +00:00
X86	[X86] Add the bizarro movsww and movzww mnemonics for the disassembler.	2018-04-13 23:57:54 +00:00
XCore