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666af50fcf
This changes MachineRegisterInfo to be initializes after parsing all instructions. This is in preparation for upcoming commits that allow the register class specification on the operand or deduce them from the MCInstrDesc. This commit removes the unused feature of having nonsequential register numbers. This was confusing anyway as the vreg numbers would be different after parsing when you had "holes" in your numbering. This patch also introduces the concept of an incomplete virtual register. An incomplete virtual register may be used during .mir parsing to construct MachineOperands without knowing the exact register class (or register bank) yet. NFC except for some error messages. Differential Revision: https://reviews.llvm.org/D22397 llvm-svn: 283848
26 lines
517 B
YAML
26 lines
517 B
YAML
# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
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# This test ensures that the MIR parser reports an error when parsing a
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# reference to an undefined virtual register.
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--- |
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define i32 @test(i32 %a) {
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entry:
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ret i32 %a
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}
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...
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---
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name: test
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr32 }
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body: |
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bb.0.entry:
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%0 = COPY %edi
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; CHECK: Cannot determine class/bank of virtual register 1 in function 'test'
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%eax = COPY %1
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RETQ %eax
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...
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