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llvm-mirror/test/CodeGen/MIR
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RamNalamothu a2306da6e0 Implement DW_CFA_LLVM_* for Heterogeneous Debugging 
Add support in MC/MIR for writing/parsing, and DebugInfo.

This is part of the Extensions for Heterogeneous Debugging defined at
https://llvm.org/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.html

Specifically the CFI instructions implemented here are defined at
https://llvm.org/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.html#cfa-definition-instructions

Reviewed By: clayborg

Differential Revision: https://reviews.llvm.org/D76877
2021-06-14 08:51:50 +05:30
..
AArch64 Implement DW_CFA_LLVM_* for Heterogeneous Debugging 2021-06-14 08:51:50 +05:30
AMDGPU AMDGPU: Move codegen test out of MIR test directory 2021-06-07 14:26:48 -04:00
ARM Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
Generic MIR: Fix missing serialization for HasTailCall 2021-03-21 13:14:04 -04:00
Hexagon
Mips
NVPTX
PowerPC
WebAssembly
X86 Reapply "[DebugInfo] Add new instruction and DIExpression operator for variadic debug values" 2021-03-05 12:32:05 +00:00
README

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.