Anshil Gandhi 7f0aeb0ac8 [AMDGPU] [CodeGen] Fold negate llvm.amdgcn.class into test mask ... Implemented the transformation of xor (llvm.amdgcn.class x, mask), -1 into llvm.amdgcn.class(x, ~mask). Added LIT tests as well. Differential Revision: https://reviews.llvm.org/D104049		2021-06-18 13:04:12 -06:00
..
AArch64	[AArch64] Add TableGen patterns to generate uaddlv	2021-06-18 17:23:26 +01:00
AMDGPU	[AMDGPU] [CodeGen] Fold negate llvm.amdgcn.class into test mask	2021-06-18 13:04:12 -06:00
ARC
ARM	Update @llvm.powi to handle different int sizes for the exponent	2021-06-17 09:38:28 +02:00
AVR
BPF
Generic	Update @llvm.powi to handle different int sizes for the exponent	2021-06-17 09:38:28 +02:00
Hexagon
Inputs
Lanai
M68k	[M68k][GloballSel] Adding initial GlobalISel infrastructure	2021-06-16 10:48:38 -06:00
Mips	Update @llvm.powi to handle different int sizes for the exponent	2021-06-17 09:38:28 +02:00
MIR	Implement DW_CFA_LLVM_* for Heterogeneous Debugging	2021-06-14 08:51:50 +05:30
MSP430
NVPTX	Update @llvm.powi to handle different int sizes for the exponent	2021-06-17 09:38:28 +02:00
PowerPC	Update @llvm.powi to handle different int sizes for the exponent	2021-06-17 09:38:28 +02:00
RISCV	test: clean up some of the RISCV tests (NFC)	2021-06-17 09:51:09 -07:00
SPARC	[SPARC] Legalize truncation and extension between fp128 and half	2021-06-13 20:05:15 +02:00
SystemZ	Update @llvm.powi to handle different int sizes for the exponent	2021-06-17 09:38:28 +02:00
Thumb	Do not generate calls to the 128-bit function __multi3() on 32-bit ARM	2021-06-11 11:45:21 +01:00
Thumb2	Update @llvm.powi to handle different int sizes for the exponent	2021-06-17 09:38:28 +02:00
VE
WebAssembly	[WebAssembly] Rename event to tag	2021-06-17 20:34:19 -07:00
WinCFGuard
WinEH
X86	Update @llvm.powi to handle different int sizes for the exponent	2021-06-17 09:38:28 +02:00
XCore	Update @llvm.powi to handle different int sizes for the exponent	2021-06-17 09:38:28 +02:00