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By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown, backends can request that LLVM to scalarize vector types for calls and returns. The MIPS vector ABI requires that vector arguments and returns are passed in integer registers. With SelectionDAG's new hooks, the MIPS backend can now handle LLVM-IR with vector types in calls and returns. E.g. 'call @foo(<4 x i32> %4)'. Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for calls and returns if vector types were not legal. If vector types were legal, a single 128bit vector argument would be assigned to a single 32 bit / 64 bit integer register. By teaching the MIPS backend to inspect the original types, it can now implement the MIPS vector ABI which requires a particular method of scalarizing vectors. Previously, the MIPS backend relied on clang to scalarize types such as "call @foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3, i32 inreg %4)". This patch enables the MIPS backend to take either form for vector types. The previous version of this patch had a "conditional move or jump depends on uninitialized value". Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur Differential Revision: https://reviews.llvm.org/D27845 llvm-svn: 305083
24 lines
755 B
LLVM
24 lines
755 B
LLVM
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32
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; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64
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declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1)
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define <2 x i32> @ctlzv2i32(<2 x i32> %x) {
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entry:
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; MIPS32: clz $2, $4
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; MIPS32: clz $3, $5
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; MIPS64-DAG: dsrl $[[A0:[0-9]+]], $4, 32
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; MIPS64-DAG: sll $[[A1:[0-9]+]], $[[A0]], 0
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; MIPS64-DAG: clz $[[R0:[0-9]+]], $[[A1]]
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; MIPS64-DAG: dsll $[[R1:[0-9]+]], $[[R0]], 32
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; MIPS64-DAG: sll $[[A2:[0-9]+]], $4, 0
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; MIPS64-DAG: clz $[[R2:[0-9]+]], $[[A2]]
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; MIPS64-DAG: dext $[[R3:[0-9]+]], $[[R2]], 0, 32
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; MIPS64-DAG: or $2, $[[R3]], $[[R1]]
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%ret = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %x, i1 true)
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ret <2 x i32> %ret
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}
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