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1b43caab05
These instructions lacked the correct predicates, were not marked as loads and stores and lacked the proper instruction mapping information. In the case of microMIPS sw(l|r)e (EVA) these instructions were using the load EVA description. Reviewers: abeserminji, smaksimovic, atanasyan Differential Revision: https://reviews.llvm.org/D45626 llvm-svn: 330326
125 lines
3.1 KiB
YAML
125 lines
3.1 KiB
YAML
# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=expand-isel-pseudos \
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# RUN: -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s
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# Test that MIPS unaligned load/store instructions can be mapped to their
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# corresponding microMIPS instructions.
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--- |
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define void @g(i32* %a, i32* %b) {
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entry:
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%0 = load i32, i32* %a, align 1
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store i32 %0, i32* %b, align 1
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ret void
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}
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define void @g2(i32* %a, i32* %b) {
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entry:
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%0 = load i32, i32* %a, align 1
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store i32 %0, i32* %b, align 1
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ret void
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}
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...
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---
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name: g
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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liveins:
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- { reg: '$a0', virtual-reg: '%0' }
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- { reg: '$a1', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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liveins: $a0, $a1
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%1:gpr32 = COPY $a1
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%0:gpr32 = COPY $a0
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%3:gpr32 = IMPLICIT_DEF
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%2:gpr32 = LWL %0, 0, %3 :: (load 4 from %ir.a, align 1)
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%4:gpr32 = LWR %0, 3, %2 :: (load 4 from %ir.a, align 1)
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SWL %4, %1, 0 :: (store 4 into %ir.b, align 1)
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SWR %4, %1, 3 :: (store 4 into %ir.b, align 1)
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RetRA
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...
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---
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name: g2
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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liveins:
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- { reg: '$a0', virtual-reg: '%0' }
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- { reg: '$a1', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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liveins: $a0, $a1
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%1:gpr32 = COPY $a1
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%0:gpr32 = COPY $a0
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%3:gpr32 = IMPLICIT_DEF
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%2:gpr32 = LWLE %0, 0, %3 :: (load 4 from %ir.a, align 1)
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%4:gpr32 = LWRE %0, 3, %2 :: (load 4 from %ir.a, align 1)
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SWLE %4, %1, 0 :: (store 4 into %ir.b, align 1)
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SWRE %4, %1, 3 :: (store 4 into %ir.b, align 1)
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RetRA
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...
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# CHECK-LABEL: g:
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# CHECK: 0: 60 24 00 00 lwl $1, 0($4)
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# CHECK: 4: 60 24 10 03 lwr $1, 3($4)
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# CHECK: 8: 60 25 80 00 swl $1, 0($5)
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# CHECK: c: 60 25 90 03 swr $1, 3($5)
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# CHECK-LABEL: g2:
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# CHECK: 14: 60 24 64 00 lwle $1, 0($4)
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# CHECK: 18: 60 24 66 03 lwre $1, 3($4)
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# CHECK: 1c: 60 25 a0 00 swle $1, 0($5)
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# CHECK: 20: 60 25 a2 03 swre $1, 3($5)
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