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861e8a0eb7
The match pattern in the definition of LXSDX is xoaddr, so the Pseudo instruction XFLOADf64 never gets selected. XFLOADf64 expands to LXSDX/LFDX post RA based on the register pressure. To avoid ambiguity, we need to remove the select pattern for LXSDX, same as what was done for LXSD. STXSDX also have the same issue. Patch by Qing Shan Zhang (steven.zhang). Differential Revision: https://reviews.llvm.org/D47178 llvm-svn: 333150
106 lines
2.3 KiB
LLVM
106 lines
2.3 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=a2 | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck %s -check-prefix=CHECK-P9
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define float @foo(i64 %a) nounwind {
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entry:
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%x = sitofp i64 %a to float
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ret float %x
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; CHECK: @foo
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; CHECK: std 3,
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; CHECK: lfd [[REG:[0-9]+]],
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; CHECK: fcfids 1, [[REG]]
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; CHECK: blr
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; CHECK-VSX: @foo
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; CHECK-VSX: std 3,
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; CHECK-VSX: lfdx [[REG:[0-9]+]],
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; CHECK-VSX: fcfids 1, [[REG]]
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; CHECK-VSX: blr
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; CHECK-P9: @foo
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; CHECK-P9: std 3,
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; CHECK-P9: lfd [[REG:[0-9]+]],
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; CHECK-P9: xscvsxdsp 1, [[REG]]
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; CHECK-P9: blr
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}
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define double @goo(i64 %a) nounwind {
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entry:
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%x = sitofp i64 %a to double
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ret double %x
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; CHECK: @goo
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; CHECK: std 3,
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; CHECK: lfd [[REG:[0-9]+]],
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; CHECK: fcfid 1, [[REG]]
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; CHECK: blr
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; CHECK-VSX: @goo
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; CHECK-VSX: std 3,
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; CHECK-VSX: lfdx [[REG:[0-9]+]],
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; CHECK-VSX: xscvsxddp 1, [[REG]]
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; CHECK-VSX: blr
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; CHECK-P9: @goo
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; CHECK-P9: std 3,
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; CHECK-P9: lfd [[REG:[0-9]+]],
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; CHECK-P9: xscvsxddp 1, [[REG]]
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; CHECK-P9: blr
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}
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define float @foou(i64 %a) nounwind {
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entry:
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%x = uitofp i64 %a to float
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ret float %x
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; CHECK: @foou
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; CHECK: std 3,
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; CHECK: lfd [[REG:[0-9]+]],
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; CHECK: fcfidus 1, [[REG]]
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; CHECK: blr
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; CHECK-VSX: @foou
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; CHECK-VSX: std 3,
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; CHECK-VSX: lfdx [[REG:[0-9]+]],
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; CHECK-VSX: fcfidus 1, [[REG]]
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; CHECK-VSX: blr
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; CHECK-P9: @foou
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; CHECK-P9: std 3,
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; CHECK-P9: lfd [[REG:[0-9]+]],
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; CHECK-P9: xscvuxdsp 1, [[REG]]
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; CHECK-P9: blr
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}
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define double @goou(i64 %a) nounwind {
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entry:
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%x = uitofp i64 %a to double
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ret double %x
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; CHECK: @goou
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; CHECK: std 3,
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; CHECK: lfd [[REG:[0-9]+]],
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; CHECK: fcfidu 1, [[REG]]
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; CHECK: blr
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; CHECK-VSX: @goou
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; CHECK-VSX: std 3,
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; CHECK-VSX: lfdx [[REG:[0-9]+]],
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; CHECK-VSX: xscvuxddp 1, [[REG]]
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; CHECK-VSX: blr
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; CHECK-P9: @goou
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; CHECK-P9: std 3,
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; CHECK-P9: lfd [[REG:[0-9]+]],
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; CHECK-P9: xscvuxddp 1, [[REG]]
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; CHECK-P9: blr
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}
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