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https://github.com/RPCS3/llvm-mirror.git
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3f9ad6b478
This re-commits everything that was pulled in r314244. The transformation is off by default (patch to enable it to follow). The code is refactored to have a single entry-point and provide fine-grained control over patterns that it selects. This patch also fixes the bugs in the original code. Everything that failed with the original patch has been re-tested with this patch (with the transformation turned on). So the patch to turn this on is soon to follow. Differential Revision: https://reviews.llvm.org/D38575 llvm-svn: 319434
122 lines
3.3 KiB
LLVM
122 lines
3.3 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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@glob = common local_unnamed_addr global i32 0, align 4
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define signext i32 @test_ineui(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: test_ineui:
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; CHECK: xor r3, r3, r4
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define signext i32 @test_ineui_sext(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: test_ineui_sext:
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; CHECK: xor r3, r3, r4
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i32 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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define signext i32 @test_ineui_z(i32 zeroext %a) {
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; CHECK-LABEL: test_ineui_z:
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; CHECK: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i32 %a, 0
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define signext i32 @test_ineui_sext_z(i32 zeroext %a) {
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; CHECK-LABEL: test_ineui_sext_z:
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; CHECK: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i32 %a, 0
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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define void @test_ineui_store(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: test_ineui_store:
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; CHECK: xor r3, r3, r4
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; CHECK: cntlzw r3, r3
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; CHECK: srwi r3, r3, 5
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; CHECK: xori r3, r3, 1
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; CHECK: stw r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i32 %a, %b
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @glob, align 4
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ret void
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}
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define void @test_ineui_sext_store(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: test_ineui_sext_store:
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; CHECK: xor r3, r3, r4
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; CHECK: cntlzw r3, r3
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; CHECK: srwi r3, r3, 5
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; CHECK: xori r3, r3, 1
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; CHECK: neg r3, r3
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; CHECK: stw r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i32 %a, %b
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%sub = sext i1 %cmp to i32
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store i32 %sub, i32* @glob, align 4
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ret void
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}
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define void @test_ineui_z_store(i32 zeroext %a) {
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; CHECK-LABEL: test_ineui_z_store:
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; CHECK: cntlzw r3, r3
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; CHECK: srwi r3, r3, 5
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; CHECK: xori r3, r3, 1
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; CHECK: stw r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i32 %a, 0
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @glob, align 4
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ret void
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}
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define void @test_ineui_sext_z_store(i32 zeroext %a) {
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; CHECK-LABEL: test_ineui_sext_z_store:
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; CHECK: cntlzw r3, r3
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; CHECK: srwi r3, r3, 5
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; CHECK: xori r3, r3, 1
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; CHECK: neg r3, r3
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; CHECK: stw r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i32 %a, 0
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%sub = sext i1 %cmp to i32
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store i32 %sub, i32* @glob, align 4
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ret void
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}
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