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llvm-mirror/test/CodeGen/MIR/PowerPC
Alex Lorenz 518df78860 Fix PR 24724 - The implicit register verifier shouldn't assume certain operand
order.

The implicit register verifier in the MIR parser should only check if the
instruction's default implicit operands are present in the instruction. It
should not check the order in which they occur.

llvm-svn: 247283
2015-09-10 14:04:34 +00:00
..
lit.local.cfg
unordered-implicit-registers.mir