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518df78860
order. The implicit register verifier in the MIR parser should only check if the instruction's default implicit operands are present in the instruction. It should not check the order in which they occur. llvm-svn: 247283
46 lines
1.2 KiB
YAML
46 lines
1.2 KiB
YAML
# RUN: llc -mtriple=powerpc64-unknown-linux-gnu -start-after machine-combiner -stop-after machine-combiner -o /dev/null %s | FileCheck %s
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# PR24724
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--- |
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define signext i32 @main(i32* %p) #0 {
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entry:
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%0 = load i32, i32* %p, align 4
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%or = or i32 0, %0
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store i32 %or, i32* %p, align 4
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%lnot.1 = icmp eq i32 undef, 0
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%lnot.ext.1 = zext i1 %lnot.1 to i32
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%shr.i.1 = lshr i32 2072, %lnot.ext.1
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%call.lobit.1 = lshr i32 %shr.i.1, 7
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%1 = and i32 %call.lobit.1, 1
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%or.1 = or i32 %1, %or
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ret i32 %or.1
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}
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attributes #0 = { nounwind "target-cpu"="ppc64" }
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...
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---
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name: main
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isSSA: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc_and_g8rc_nox0 }
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- { id: 1, class: gprc }
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- { id: 2, class: gprc }
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- { id: 3, class: gprc }
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- { id: 4, class: g8rc }
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liveins:
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- { reg: '%x3', virtual-reg: '%0' }
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body: |
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bb.0.entry:
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liveins: %x3
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%0 = COPY %x3
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%1 = LWZ 0, %0 :: (load 4 from %ir.p)
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%2 = LI 0
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%3 = RLWIMI %2, killed %1, 0, 0, 31
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%4 = EXTSW_32_64 killed %3
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%x3 = COPY %4
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; CHECK: BLR8 implicit %lr8, implicit %rm, implicit %x3
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BLR8 implicit %lr8, implicit %rm, implicit %x3
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...
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