Saleem Abdulrasool 8388ecd074 ARM: try harder to detect non-IT eligible instructions ... For many Thumb-1 register register instructions, setting the CPSR is not permitted inside an IT block. We would not correctly flag those instructions. The previous change to identify this scenario was insufficient as it did not actually catch all the instances. The current list is formed by manual inspection of the ARMv6M ARM. The change to the Thumb2 IT block test is due to the fact that the new more stringent checking of the MIs results in the If Conversion pass being prevented from executing (since not all the instructions in the BB are predicable). This results in code gen changes. Thanks to Tim Northover for pointing out that the previous patch was insufficient and hinting that the use of the v6M ARM would be much easier to use than the v7 or v8! llvm-svn: 215382		2014-08-11 20:13:25 +00:00
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AArch64	In Machine CSE pass, the source register of a COPY machine instruction can	2014-08-11 05:17:19 +00:00
ARM	ARM: try harder to detect non-IT eligible instructions	2014-08-11 20:13:25 +00:00
CPP
Generic	Use "weak alias" instead of "alias weak"	2014-07-30 22:51:54 +00:00
Hexagon	DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.	2014-08-06 00:21:25 +00:00
Inputs
Mips	Add support for scalarizing cttz_zero_undef	2014-08-10 22:49:54 +00:00
MSP430
NVPTX	[NVPTX] Add some extra tests for mul.wide to test non-power-of-two source types	2014-07-23 20:23:49 +00:00
PowerPC	Provide an implementation of getNoopForMachoTarget for PPC, otherwise	2014-08-08 19:13:23 +00:00
R600	R600/SI: Custom lower CONCAT_VECTORS	2014-08-09 01:06:56 +00:00
SPARC
SystemZ
Thumb	[ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly	2014-08-02 05:40:40 +00:00
Thumb2	ARM: do not generate BLX instructions on Cortex-M CPUs.	2014-08-06 11:13:14 +00:00
X86	[FastISel][X86] Fix INC/DEC optimization (r215230)	2014-08-08 18:47:04 +00:00
XCore