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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
30 lines
578 B
YAML
30 lines
578 B
YAML
# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
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--- |
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define i32 @test(i32 %a) {
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entry:
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%b = alloca i32
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store i32 %a, i32* %b
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%c = load i32, i32* %b
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ret i32 %c
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}
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...
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---
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name: test
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr32 }
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frameInfo:
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maxAlignment: 4
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stack:
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- { id: 0, name: b, size: 4, alignment: 4 }
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body: |
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bb.0.entry:
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%0 = COPY $edi
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; CHECK: [[@LINE+1]]:13: use of undefined stack object '%stack.2'
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MOV32mr %stack.2, 1, _, 0, _, %0
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$eax = COPY %0
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RETQ $eax
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...
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