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02ccf5b7ea
This patch implements the Cortex-A57 scheduling model. The main code is in ARMScheduleA57.td, ARMScheduleA57WriteRes.td. Small changes in cpp,.h files to support required scheduling predicates. Scheduling model implemented according to: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf. Patch by : Andrew Zhogin (submitted on his behalf, as requested). Rewiewed by: Renato Golin, Diana Picus, Javed Absar, Kristof Beyls. Differential Revision: https://reviews.llvm.org/D28152 llvm-svn: 304530
37 lines
1.1 KiB
LLVM
37 lines
1.1 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
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; N=3 STMIA_UPD should have latency 2cyc and writeback latency 1cyc
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; CHECK: ********** MI Scheduling **********
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; We need second, post-ra scheduling to have STM instruction combined from single-stores
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; CHECK: ********** MI Scheduling **********
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; CHECK: schedule starting
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; CHECK: STMIA_UPD
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; CHECK: rdefs left
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; CHECK-NEXT: Latency : 2
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; CHECK: Successors
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; CHECK: data
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; CHECK-SAME: Latency=1
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define i32 @bar(i32 %v0, i32 %v1, i32 %v2, i32* %addr) {
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%addr.1 = getelementptr i32, i32* %addr, i32 0
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store i32 %v0, i32* %addr.1
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%addr.2 = getelementptr i32, i32* %addr, i32 1
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store i32 %v1, i32* %addr.2
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%addr.3 = getelementptr i32, i32* %addr, i32 2
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store i32 %v2, i32* %addr.3
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%ptr_after = getelementptr i32, i32* %addr, i32 3
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%val = ptrtoint i32* %ptr_after to i32
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%rv1 = mul i32 %val, %v0
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%rv2 = mul i32 %rv1, %v1
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%rv3 = mul i32 %rv2, %v2
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ret i32 %rv3
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}
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