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https://github.com/RPCS3/llvm-mirror.git
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32aba74592
Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro Reviewed By: rengolin, fhahn Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45371 llvm-svn: 329681
523 lines
17 KiB
TableGen
523 lines
17 KiB
TableGen
//=-- SVEInstrFormats.td - AArch64 SVE Instruction classes -*- tablegen -*--=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// AArch64 Scalable Vector Extension (SVE) Instruction Class Definitions.
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//
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//===----------------------------------------------------------------------===//
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def SVEPatternOperand : AsmOperandClass {
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let Name = "SVEPattern";
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let ParserMethod = "tryParseSVEPattern";
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let PredicateMethod = "isSVEPattern";
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let RenderMethod = "addImmOperands";
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let DiagnosticType = "InvalidSVEPattern";
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}
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def sve_pred_enum : Operand<i32>, ImmLeaf<i32, [{
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return (((uint32_t)Imm) < 32);
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}]> {
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let PrintMethod = "printSVEPattern";
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let ParserMatchClass = SVEPatternOperand;
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}
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class SVELogicalImmOperand<int Width> : AsmOperandClass {
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let Name = "SVELogicalImm" # Width;
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let DiagnosticType = "LogicalSecondSource";
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let PredicateMethod = "isLogicalImm<int" # Width # "_t>";
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let RenderMethod = "addLogicalImmOperands<int" # Width # "_t>";
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}
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def sve_logical_imm8 : Operand<i64> {
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let ParserMatchClass = SVELogicalImmOperand<8>;
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let PrintMethod = "printLogicalImm<int8_t>";
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let MCOperandPredicate = [{
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if (!MCOp.isImm())
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return false;
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int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
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return AArch64_AM::isSVEMaskOfIdenticalElements<int8_t>(Val);
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}];
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}
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def sve_logical_imm16 : Operand<i64> {
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let ParserMatchClass = SVELogicalImmOperand<16>;
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let PrintMethod = "printLogicalImm<int16_t>";
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let MCOperandPredicate = [{
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if (!MCOp.isImm())
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return false;
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int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
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return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val);
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}];
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}
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def sve_logical_imm32 : Operand<i64> {
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let ParserMatchClass = SVELogicalImmOperand<32>;
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let PrintMethod = "printLogicalImm<int32_t>";
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let MCOperandPredicate = [{
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if (!MCOp.isImm())
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return false;
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int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
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return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val);
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}];
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}
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//===----------------------------------------------------------------------===//
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class SVELogicalImmNotOperand<int Width> : AsmOperandClass {
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let Name = "SVELogicalImm" # Width # "Not";
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let DiagnosticType = "LogicalSecondSource";
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let PredicateMethod = "isLogicalImm<int" # Width # "_t>";
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let RenderMethod = "addLogicalImmNotOperands<int" # Width # "_t>";
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}
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def sve_logical_imm8_not : Operand<i64> {
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let ParserMatchClass = SVELogicalImmNotOperand<8>;
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}
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def sve_logical_imm16_not : Operand<i64> {
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let ParserMatchClass = SVELogicalImmNotOperand<16>;
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}
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def sve_logical_imm32_not : Operand<i64> {
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let ParserMatchClass = SVELogicalImmNotOperand<32>;
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}
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//===----------------------------------------------------------------------===//
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// SVE PTrue - These are used extensively throughout the pattern matching so
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// it's important we define them first.
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//===----------------------------------------------------------------------===//
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class sve_int_ptrue<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty>
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: I<(outs pprty:$Pd), (ins sve_pred_enum:$pattern),
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asm, "\t$Pd, $pattern",
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"",
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[]>, Sched<[]> {
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bits<4> Pd;
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bits<5> pattern;
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let Inst{31-24} = 0b00100101;
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let Inst{23-22} = sz8_64;
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let Inst{21-19} = 0b011;
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let Inst{18-17} = opc{2-1};
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let Inst{16} = opc{0};
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let Inst{15-10} = 0b111000;
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let Inst{9-5} = pattern;
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let Inst{4} = 0b0;
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let Inst{3-0} = Pd;
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let Defs = !if(!eq (opc{0}, 1), [NZCV], []);
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}
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multiclass sve_int_ptrue<bits<3> opc, string asm> {
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def _B : sve_int_ptrue<0b00, opc, asm, PPR8>;
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def _H : sve_int_ptrue<0b01, opc, asm, PPR16>;
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def _S : sve_int_ptrue<0b10, opc, asm, PPR32>;
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def _D : sve_int_ptrue<0b11, opc, asm, PPR64>;
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def : InstAlias<asm # "\t$Pd",
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(!cast<Instruction>(NAME # _B) PPR8:$Pd, 0b11111), 1>;
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def : InstAlias<asm # "\t$Pd",
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(!cast<Instruction>(NAME # _H) PPR16:$Pd, 0b11111), 1>;
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def : InstAlias<asm # "\t$Pd",
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(!cast<Instruction>(NAME # _S) PPR32:$Pd, 0b11111), 1>;
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def : InstAlias<asm # "\t$Pd",
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(!cast<Instruction>(NAME # _D) PPR64:$Pd, 0b11111), 1>;
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}
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let Predicates = [HasSVE] in {
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defm PTRUE : sve_int_ptrue<0b000, "ptrue">;
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defm PTRUES : sve_int_ptrue<0b001, "ptrues">;
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}
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//===----------------------------------------------------------------------===//
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// SVE Permute - Cross Lane Group
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//===----------------------------------------------------------------------===//
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class sve_int_perm_dup_r<bits<2> sz8_64, string asm, ZPRRegOp zprty,
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RegisterClass srcRegType>
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: I<(outs zprty:$Zd), (ins srcRegType:$Rn),
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asm, "\t$Zd, $Rn",
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"",
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[]>, Sched<[]> {
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bits<5> Rn;
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bits<5> Zd;
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let Inst{31-24} = 0b00000101;
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let Inst{23-22} = sz8_64;
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let Inst{21-10} = 0b100000001110;
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let Inst{9-5} = Rn;
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let Inst{4-0} = Zd;
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}
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multiclass sve_int_perm_dup_r<string asm> {
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def _B : sve_int_perm_dup_r<0b00, asm, ZPR8, GPR32sp>;
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def _H : sve_int_perm_dup_r<0b01, asm, ZPR16, GPR32sp>;
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def _S : sve_int_perm_dup_r<0b10, asm, ZPR32, GPR32sp>;
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def _D : sve_int_perm_dup_r<0b11, asm, ZPR64, GPR64sp>;
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def : InstAlias<"mov $Zd, $Rn",
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(!cast<Instruction>(NAME # _B) ZPR8:$Zd, GPR32sp:$Rn), 1>;
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def : InstAlias<"mov $Zd, $Rn",
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(!cast<Instruction>(NAME # _H) ZPR16:$Zd, GPR32sp:$Rn), 1>;
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def : InstAlias<"mov $Zd, $Rn",
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(!cast<Instruction>(NAME # _S) ZPR32:$Zd, GPR32sp:$Rn), 1>;
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def : InstAlias<"mov $Zd, $Rn",
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(!cast<Instruction>(NAME # _D) ZPR64:$Zd, GPR64sp:$Rn), 1>;
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}
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//===----------------------------------------------------------------------===//
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// SVE Logical Mask Immediate Group
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//===----------------------------------------------------------------------===//
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class sve_int_log_imm<bits<2> opc, string asm>
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: I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, logical_imm64:$imms13),
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asm, "\t$Zdn, $_Zdn, $imms13",
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"", []>, Sched<[]> {
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bits<5> Zdn;
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bits<13> imms13;
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let Inst{31-24} = 0b00000101;
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let Inst{23-22} = opc;
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let Inst{21-18} = 0b0000;
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let Inst{17-5} = imms13;
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let Inst{4-0} = Zdn;
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let Constraints = "$Zdn = $_Zdn";
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let DecoderMethod = "DecodeSVELogicalImmInstruction";
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}
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multiclass sve_int_log_imm<bits<2> opc, string asm, string alias> {
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def NAME : sve_int_log_imm<opc, asm>;
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def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
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(!cast<Instruction>(NAME) ZPR8:$Zdn, sve_logical_imm8:$imm), 4>;
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def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
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(!cast<Instruction>(NAME) ZPR16:$Zdn, sve_logical_imm16:$imm), 3>;
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def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
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(!cast<Instruction>(NAME) ZPR32:$Zdn, sve_logical_imm32:$imm), 2>;
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def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
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(!cast<Instruction>(NAME) ZPR8:$Zdn, sve_logical_imm8_not:$imm), 0>;
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def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
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(!cast<Instruction>(NAME) ZPR16:$Zdn, sve_logical_imm16_not:$imm), 0>;
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def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
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(!cast<Instruction>(NAME) ZPR32:$Zdn, sve_logical_imm32_not:$imm), 0>;
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def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
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(!cast<Instruction>(NAME) ZPR64:$Zdn, logical_imm64_not:$imm), 0>;
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}
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//===----------------------------------------------------------------------===//
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// SVE Integer Arithmetic - Unpredicated Group.
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//===----------------------------------------------------------------------===//
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class sve_int_bin_cons_arit_0<bits<2> sz8_64, bits<3> opc, string asm,
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ZPRRegOp zprty>
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: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
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asm, "\t$Zd, $Zn, $Zm",
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"", []>, Sched<[]> {
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bits<5> Zd;
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bits<5> Zm;
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bits<5> Zn;
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let Inst{31-24} = 0b00000100;
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let Inst{23-22} = sz8_64;
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let Inst{21} = 0b1;
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let Inst{20-16} = Zm;
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let Inst{15-13} = 0b000;
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let Inst{12-10} = opc;
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let Inst{9-5} = Zn;
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let Inst{4-0} = Zd;
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}
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multiclass sve_int_bin_cons_arit_0<bits<3> opc, string asm> {
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def _B : sve_int_bin_cons_arit_0<0b00, opc, asm, ZPR8>;
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def _H : sve_int_bin_cons_arit_0<0b01, opc, asm, ZPR16>;
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def _S : sve_int_bin_cons_arit_0<0b10, opc, asm, ZPR32>;
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def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64>;
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}
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//===----------------------------------------------------------------------===//
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// SVE Stack Allocation Group
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//===----------------------------------------------------------------------===//
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class sve_int_arith_vl<bit opc, string asm>
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: I<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, simm6_32b:$imm6),
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asm, "\t$Rd, $Rn, $imm6",
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"",
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[]>, Sched<[]> {
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bits<5> Rd;
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bits<5> Rn;
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bits<6> imm6;
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let Inst{31-23} = 0b000001000;
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let Inst{22} = opc;
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let Inst{21} = 0b1;
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let Inst{20-16} = Rn;
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let Inst{15-11} = 0b01010;
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let Inst{10-5} = imm6;
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let Inst{4-0} = Rd;
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}
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class sve_int_read_vl_a<bit op, bits<5> opc2, string asm>
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: I<(outs GPR64:$Rd), (ins simm6_32b:$imm6),
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asm, "\t$Rd, $imm6",
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"",
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[]>, Sched<[]> {
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bits<5> Rd;
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bits<6> imm6;
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let Inst{31-23} = 0b000001001;
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let Inst{22} = op;
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let Inst{21} = 0b1;
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let Inst{20-16} = opc2{4-0};
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let Inst{15-11} = 0b01010;
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let Inst{10-5} = imm6;
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let Inst{4-0} = Rd;
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}
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//===----------------------------------------------------------------------===//
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// SVE Permute - In Lane Group
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//===----------------------------------------------------------------------===//
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class sve_int_perm_bin_perm_zz<bits<3> opc, bits<2> sz8_64, string asm,
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ZPRRegOp zprty>
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: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
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asm, "\t$Zd, $Zn, $Zm",
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"",
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[]>, Sched<[]> {
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bits<5> Zd;
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bits<5> Zm;
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bits<5> Zn;
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let Inst{31-24} = 0b00000101;
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let Inst{23-22} = sz8_64;
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let Inst{21} = 0b1;
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let Inst{20-16} = Zm;
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let Inst{15-13} = 0b011;
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let Inst{12-10} = opc;
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let Inst{9-5} = Zn;
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let Inst{4-0} = Zd;
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}
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multiclass sve_int_perm_bin_perm_zz<bits<3> opc, string asm> {
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def _B : sve_int_perm_bin_perm_zz<opc, 0b00, asm, ZPR8>;
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def _H : sve_int_perm_bin_perm_zz<opc, 0b01, asm, ZPR16>;
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def _S : sve_int_perm_bin_perm_zz<opc, 0b10, asm, ZPR32>;
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def _D : sve_int_perm_bin_perm_zz<opc, 0b11, asm, ZPR64>;
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}
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//===----------------------------------------------------------------------===//
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// SVE Integer Arithmetic - Binary Predicated Group
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//===----------------------------------------------------------------------===//
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class sve_int_bin_pred_arit_log<bits<2> sz8_64, bits<2> fmt, bits<3> opc,
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string asm, ZPRRegOp zprty>
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: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
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asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> {
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bits<3> Pg;
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bits<5> Zdn;
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bits<5> Zm;
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let Inst{31-24} = 0b00000100;
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let Inst{23-22} = sz8_64;
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let Inst{21} = 0b0;
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let Inst{20-19} = fmt;
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let Inst{18-16} = opc;
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let Inst{15-13} = 0b000;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Zm;
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let Inst{4-0} = Zdn;
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let Constraints = "$Zdn = $_Zdn";
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}
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multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm> {
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def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>;
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def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>;
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def _S : sve_int_bin_pred_arit_log<0b10, 0b00, opc, asm, ZPR32>;
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def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>;
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}
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//===----------------------------------------------------------------------===//
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//SVE Index Generation Group
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//===----------------------------------------------------------------------===//
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class sve_int_index_ii<bits<2> sz8_64, string asm, ZPRRegOp zprty,
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Operand imm_ty>
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: I<(outs zprty:$Zd), (ins imm_ty:$imm5, imm_ty:$imm5b),
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asm, "\t$Zd, $imm5, $imm5b",
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"", []>, Sched<[]> {
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bits<5> Zd;
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bits<5> imm5;
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bits<5> imm5b;
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let Inst{31-24} = 0b00000100;
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let Inst{23-22} = sz8_64;
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let Inst{21} = 0b1;
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let Inst{20-16} = imm5b;
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let Inst{15-10} = 0b010000;
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let Inst{9-5} = imm5;
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let Inst{4-0} = Zd;
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}
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multiclass sve_int_index_ii<string asm> {
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def _B : sve_int_index_ii<0b00, asm, ZPR8, simm5_32b>;
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def _H : sve_int_index_ii<0b01, asm, ZPR16, simm5_32b>;
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def _S : sve_int_index_ii<0b10, asm, ZPR32, simm5_32b>;
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def _D : sve_int_index_ii<0b11, asm, ZPR64, simm5_64b>;
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}
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class sve_int_index_ir<bits<2> sz8_64, string asm, ZPRRegOp zprty,
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RegisterClass srcRegType, Operand imm_ty>
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: I<(outs zprty:$Zd), (ins imm_ty:$imm5, srcRegType:$Rm),
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asm, "\t$Zd, $imm5, $Rm",
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"", []>, Sched<[]> {
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bits<5> Rm;
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bits<5> Zd;
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bits<5> imm5;
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let Inst{31-24} = 0b00000100;
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let Inst{23-22} = sz8_64;
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let Inst{21} = 0b1;
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let Inst{20-16} = Rm;
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let Inst{15-10} = 0b010010;
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let Inst{9-5} = imm5;
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let Inst{4-0} = Zd;
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}
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multiclass sve_int_index_ir<string asm> {
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def _B : sve_int_index_ir<0b00, asm, ZPR8, GPR32, simm5_32b>;
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def _H : sve_int_index_ir<0b01, asm, ZPR16, GPR32, simm5_32b>;
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def _S : sve_int_index_ir<0b10, asm, ZPR32, GPR32, simm5_32b>;
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def _D : sve_int_index_ir<0b11, asm, ZPR64, GPR64, simm5_64b>;
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}
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class sve_int_index_ri<bits<2> sz8_64, string asm, ZPRRegOp zprty,
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RegisterClass srcRegType, Operand imm_ty>
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: I<(outs zprty:$Zd), (ins srcRegType:$Rn, imm_ty:$imm5),
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asm, "\t$Zd, $Rn, $imm5",
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"", []>, Sched<[]> {
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bits<5> Rn;
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bits<5> Zd;
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bits<5> imm5;
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let Inst{31-24} = 0b00000100;
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let Inst{23-22} = sz8_64;
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let Inst{21} = 0b1;
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let Inst{20-16} = imm5;
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let Inst{15-10} = 0b010001;
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let Inst{9-5} = Rn;
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let Inst{4-0} = Zd;
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}
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|
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multiclass sve_int_index_ri<string asm> {
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def _B : sve_int_index_ri<0b00, asm, ZPR8, GPR32, simm5_32b>;
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def _H : sve_int_index_ri<0b01, asm, ZPR16, GPR32, simm5_32b>;
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def _S : sve_int_index_ri<0b10, asm, ZPR32, GPR32, simm5_32b>;
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def _D : sve_int_index_ri<0b11, asm, ZPR64, GPR64, simm5_64b>;
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}
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|
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class sve_int_index_rr<bits<2> sz8_64, string asm, ZPRRegOp zprty,
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RegisterClass srcRegType>
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: I<(outs zprty:$Zd), (ins srcRegType:$Rn, srcRegType:$Rm),
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asm, "\t$Zd, $Rn, $Rm",
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|
"", []>, Sched<[]> {
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|
bits<5> Zd;
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|
bits<5> Rm;
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|
bits<5> Rn;
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|
let Inst{31-24} = 0b00000100;
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|
let Inst{23-22} = sz8_64;
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|
let Inst{21} = 0b1;
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let Inst{20-16} = Rm;
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|
let Inst{15-10} = 0b010011;
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|
let Inst{9-5} = Rn;
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|
let Inst{4-0} = Zd;
|
|
}
|
|
|
|
multiclass sve_int_index_rr<string asm> {
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def _B : sve_int_index_rr<0b00, asm, ZPR8, GPR32>;
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|
def _H : sve_int_index_rr<0b01, asm, ZPR16, GPR32>;
|
|
def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>;
|
|
def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SVE Shift by Immediate - Unpredicated Group
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class sve_int_bin_cons_shift_b<bits<4> tsz8_64, bits<2> opc, string asm,
|
|
ZPRRegOp zprty, Operand immtype>
|
|
: I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$imm),
|
|
asm, "\t$Zd, $Zn, $imm",
|
|
"", []>, Sched<[]> {
|
|
bits<5> Zd;
|
|
bits<5> Zn;
|
|
bits<6> imm;
|
|
let Inst{31-24} = 0b00000100;
|
|
let Inst{23-22} = tsz8_64{3-2};
|
|
let Inst{21} = 0b1;
|
|
let Inst{20-19} = tsz8_64{1-0};
|
|
let Inst{18-16} = imm{2-0}; // imm3
|
|
let Inst{15-12} = 0b1001;
|
|
let Inst{11-10} = opc;
|
|
let Inst{9-5} = Zn;
|
|
let Inst{4-0} = Zd;
|
|
}
|
|
|
|
multiclass sve_int_bin_cons_shift_b_left<bits<2> opc, string asm> {
|
|
def _B : sve_int_bin_cons_shift_b<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>;
|
|
def _H : sve_int_bin_cons_shift_b<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> {
|
|
let Inst{19} = imm{3};
|
|
}
|
|
def _S : sve_int_bin_cons_shift_b<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> {
|
|
let Inst{20-19} = imm{4-3};
|
|
}
|
|
def _D : sve_int_bin_cons_shift_b<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> {
|
|
let Inst{22} = imm{5};
|
|
let Inst{20-19} = imm{4-3};
|
|
}
|
|
}
|
|
|
|
multiclass sve_int_bin_cons_shift_b_right<bits<2> opc, string asm> {
|
|
def _B : sve_int_bin_cons_shift_b<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
|
|
def _H : sve_int_bin_cons_shift_b<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
|
|
let Inst{19} = imm{3};
|
|
}
|
|
def _S : sve_int_bin_cons_shift_b<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
|
|
let Inst{20-19} = imm{4-3};
|
|
}
|
|
def _D : sve_int_bin_cons_shift_b<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
|
|
let Inst{22} = imm{5};
|
|
let Inst{20-19} = imm{4-3};
|
|
}
|
|
}
|
|
//===----------------------------------------------------------------------===//
|
|
// SVE Permute - Predicates Group
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class sve_int_perm_bin_perm_pp<bits<3> opc, bits<2> sz8_64, string asm,
|
|
PPRRegOp pprty>
|
|
: I<(outs pprty:$Pd), (ins pprty:$Pn, pprty:$Pm),
|
|
asm, "\t$Pd, $Pn, $Pm",
|
|
"",
|
|
[]>, Sched<[]> {
|
|
bits<4> Pd;
|
|
bits<4> Pm;
|
|
bits<4> Pn;
|
|
let Inst{31-24} = 0b00000101;
|
|
let Inst{23-22} = sz8_64;
|
|
let Inst{21-20} = 0b10;
|
|
let Inst{19-16} = Pm;
|
|
let Inst{15-13} = 0b010;
|
|
let Inst{12-10} = opc;
|
|
let Inst{9} = 0b0;
|
|
let Inst{8-5} = Pn;
|
|
let Inst{4} = 0b0;
|
|
let Inst{3-0} = Pd;
|
|
}
|
|
|
|
multiclass sve_int_perm_bin_perm_pp<bits<3> opc, string asm> {
|
|
def _B : sve_int_perm_bin_perm_pp<opc, 0b00, asm, PPR8>;
|
|
def _H : sve_int_perm_bin_perm_pp<opc, 0b01, asm, PPR16>;
|
|
def _S : sve_int_perm_bin_perm_pp<opc, 0b10, asm, PPR32>;
|
|
def _D : sve_int_perm_bin_perm_pp<opc, 0b11, asm, PPR64>;
|
|
}
|