Geoff Berry eef4029a4d [AArch64][Falkor] Fix bug in Falkor HWPF collision avoidance pass. ... Summary: When inserting MOVs to avoid Falkor HWPF collisions, the non-base register operand of load instructions (e.g. a register offset) was not being considered live, so it could potentially have been used as a scratch register, clobbering the actual offset value. Reviewers: mcrosier Subscribers: rengolin, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45502 llvm-svn: 329761		2018-04-10 21:43:03 +00:00
..
AsmParser	AArch64: diagnose unpredictable store-exclusive instructions	2018-04-10 11:04:29 +00:00
Disassembler	[AArch64][SVE] Asm: Add AND_ZI instructions and aliases	2018-02-06 13:13:21 +00:00
InstPrinter	[AArch64][AsmParser] NFC: Generalize LogicalImm[Not](32|64) code	2018-01-29 13:05:38 +00:00
MCTargetDesc	Recommit r329716 "Add missing nullptr check before getSection() to AArch64MachObjectWriter::recordRelocation"	2018-04-10 19:46:43 +00:00
TargetInfo
Utils	[AArch64][SVE] Asm: Predicate patterns	2018-01-22 10:46:00 +00:00
AArch64.h
AArch64.td	[PATCH] [AArch64] Add new target feature to fuse conditional select	2018-02-23 19:27:43 +00:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp	[AArch64] Change std::sort to llvm::sort in response to r327219	2018-04-04 18:20:28 +00:00
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp
AArch64CallingConvention.h
AArch64CallingConvention.td	AArch64: Implement support for the shadowcallstack attribute.	2018-04-04 21:55:44 +00:00
AArch64CallLowering.cpp	[IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer.	2018-03-29 17:21:10 +00:00
AArch64CallLowering.h
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp	Revert "[CodeGen] Move printing '\n' from MachineInstr::print to MachineBasicBlock::print"	2018-02-19 15:08:49 +00:00
AArch64CondBrTuning.cpp
AArch64ConditionalCompares.cpp
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandPseudoInsts.cpp	[AArch64] Fold adds with tprel_lo12_nc and secrel_lo12 into a following ldr/str	2018-03-12 18:47:43 +00:00
AArch64FalkorHWPFFix.cpp	[AArch64][Falkor] Fix bug in Falkor HWPF collision avoidance pass.	2018-04-10 21:43:03 +00:00
AArch64FastISel.cpp	[IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer.	2018-03-29 17:21:10 +00:00
AArch64FrameLowering.cpp	[AArch64] Use FP to access the emergency spill slot	2018-04-10 11:29:40 +00:00
AArch64FrameLowering.h
AArch64GenRegisterBankInfo.def
AArch64InstrAtomics.td	[AArch64] Improve v8.1-A code-gen for atomic load-and	2018-02-12 17:03:11 +00:00
AArch64InstrFormats.td	[AArch64][SVE] Asm: Add support for SVE INDEX instructions.	2018-04-10 07:01:53 +00:00
AArch64InstrInfo.cpp	[MachineOutliner] Keep track of fns that use a redzone in AArch64FunctionInfo	2018-04-03 21:56:10 +00:00
AArch64InstrInfo.h	[MachineOutliner] Add useMachineOutliner target hook	2018-04-04 19:13:31 +00:00
AArch64InstrInfo.td	[AArch64] Add patterns matching (fabs (fsub x y)) to (fabd x y)	2018-04-04 10:12:53 +00:00
AArch64InstructionSelector.cpp	[AArch64][GlobalISel] When copying from a gpr32 to an fpr16 reg, convert to fpr32 first.	2018-02-20 05:11:57 +00:00
AArch64ISelDAGToDAG.cpp	Revert r329611, "AArch64: Allow offsets to be folded into addresses with ELF."	2018-04-10 16:19:30 +00:00
AArch64ISelLowering.cpp	[AArch64] Fix isel failure when BUILD_PAIR nodes are left over.	2018-04-10 19:01:58 +00:00
AArch64ISelLowering.h	[AArch64] Don't reduce the width of loads if it prevents combining a shift	2018-03-23 14:47:07 +00:00
AArch64LegalizerInfo.cpp	[globalisel][legalizerinfo] Add support for the Lower action in getActionDefinitionsBuilder() and use it in AArch64.	2018-04-09 21:10:09 +00:00
AArch64LegalizerInfo.h
AArch64LoadStoreOptimizer.cpp	[CodeGen] Add a new pass for PostRA sink	2018-03-22 20:06:47 +00:00
AArch64MachineFunctionInfo.h	[MachineOutliner] Keep track of fns that use a redzone in AArch64FunctionInfo	2018-04-03 21:56:10 +00:00
AArch64MacroFusion.cpp	[PATCH] [AArch64] Add new target feature to fuse conditional select	2018-02-23 19:27:43 +00:00
AArch64MacroFusion.h
AArch64MCInstLower.cpp	Move TargetLoweringObjectFile from CodeGen to Target to fix layering	2018-03-23 23:58:19 +00:00
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp
AArch64RedundantCopyElimination.cpp
AArch64RegisterBankInfo.cpp
AArch64RegisterBankInfo.h
AArch64RegisterBanks.td
AArch64RegisterInfo.cpp	AArch64: Implement support for the shadowcallstack attribute.	2018-04-04 21:55:44 +00:00
AArch64RegisterInfo.h	[AArch64] Implement dynamic stack probing for windows	2018-02-17 14:26:32 +00:00
AArch64RegisterInfo.td
AArch64SchedA53.td	[AArch64] Clean-up a few over-eager regexps in models.	2018-03-23 11:00:42 +00:00
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64SchedExynosM1.td	[AArch64][NFC] Make all ProcResource definitions include their SchedModel.	2018-02-01 12:12:01 +00:00
AArch64SchedExynosM3.td	[AArch64] Adjust the cost model for Exynos M3	2018-04-03 22:57:17 +00:00
AArch64SchedFalkor.td	[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.	2018-03-18 19:56:15 +00:00
AArch64SchedFalkorDetails.td	[AArch64][Falkor] Correct load/store increment scheduling details	2018-03-20 13:46:35 +00:00
AArch64SchedKryo.td	[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.	2018-03-18 19:56:15 +00:00
AArch64SchedKryoDetails.td
AArch64SchedThunderX2T99.td	[AArch64] Clean-up a few over-eager regexps in models.	2018-03-23 11:00:42 +00:00
AArch64SchedThunderX.td	[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.	2018-03-18 19:56:15 +00:00
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h
AArch64SIMDInstrOpt.cpp	[TargetSchedule] shrink interface for init(); NFCI	2018-04-08 19:56:04 +00:00
AArch64StorePairSuppress.cpp	[TargetSchedule] shrink interface for init(); NFCI	2018-04-08 19:56:04 +00:00
AArch64Subtarget.cpp	AArch64: Implement support for the shadowcallstack attribute.	2018-04-04 21:55:44 +00:00
AArch64Subtarget.h	[PATCH] [AArch64] Add new target feature to fuse conditional select	2018-02-23 19:27:43 +00:00
AArch64SVEInstrInfo.td	[AArch64][SVE] Asm: Add support for unpredicated LSL/LSR (shift by immediate) instructions.	2018-04-10 10:03:13 +00:00
AArch64SystemOperands.td	[AArch64] Fix spelling of ICH_ELRSR_EL2 system register	2018-02-06 09:39:04 +00:00
AArch64TargetMachine.cpp	Plumb useAA through TargetTransformInfo to remove Transforms->CodeGen header dependency	2018-03-28 22:28:50 +00:00
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h	Move TargetLoweringObjectFile from CodeGen to Target to fix layering	2018-03-23 23:58:19 +00:00
AArch64TargetTransformInfo.cpp	[AArch64] Implement getArithmeticReductionCost	2018-03-16 11:34:15 +00:00
AArch64TargetTransformInfo.h	[AArch64] Implement getArithmeticReductionCost	2018-03-16 11:34:15 +00:00
CMakeLists.txt	Sort targetgen calls in lib/Target/*/CMakeLists.	2018-04-04 12:37:44 +00:00
LLVMBuild.txt
SVEInstrFormats.td	[AArch64][SVE] Asm: Add support for unpredicated LSL/LSR (shift by immediate) instructions.	2018-04-10 10:03:13 +00:00