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Code Issues Projects Releases Wiki Activity
llvm-mirror/test/CodeGen
History
Matt Arsenault 0e86c890f0 GlobalISel: Support legalizing G_CONSTANT with irregular breakdown 
llvm-svn: 358109
2019-04-10 17:27:53 +00:00
..
AArch64
GlobalISel: Support legalizing G_CONSTANT with irregular breakdown
2019-04-10 17:27:53 +00:00
AMDGPU
GlobalISel: Support legalizing G_CONSTANT with irregular breakdown
2019-04-10 17:27:53 +00:00
ARC
[ARC] Add ARCOptAddrMode pass to generate postincrement loads/stores.
2019-03-20 20:06:21 +00:00
ARM
[ARM] [FIX] Add missing f16 vector operations lowering
2019-04-10 13:28:06 +00:00
AVR
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BPF
[BPF] add proper multi-dimensional array support
2019-03-28 21:59:49 +00:00
Generic
Fix nondeterminism introduced in r353954
2019-03-26 12:18:08 +00:00
Hexagon
[Hexagon] Remove fcmp undef from reduced tests
2019-03-29 19:14:52 +00:00
Inputs
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Lanai
…
Mips
[MIPS GlobalISel] Select floating point arithmetic operations
2019-04-03 14:12:59 +00:00
MIR
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
MSP430
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NVPTX
[NVPTX] Fix the codegen for llvm.round.
2019-04-01 16:10:26 +00:00
PowerPC
[PowerPC] initialize SchedModel according to platform.
2019-04-09 01:25:25 +00:00
RISCV
[RISCV] Implement adding a displacement to a BlockAddress
2019-04-05 08:40:57 +00:00
SPARC
[Sparc] Fix incorrect MI insertion position for spilling f128.
2019-04-10 01:56:32 +00:00
SystemZ
[DAGCombiner][X86][SystemZ] Canonicalize SSUBO with immediate RHS to SADDO by negating the immediate.
2019-04-09 18:33:56 +00:00
Thumb
[ARM] Optimize expressions like "return x != 0;" for Thumb1.
2019-04-02 00:01:23 +00:00
Thumb2
[ARM] Add missing memory operands to a bunch of instructions.
2019-03-25 22:42:30 +00:00
WebAssembly
[WebAssembly] Add new explicit relocation types for PIC relocations
2019-04-04 17:43:50 +00:00
WinCFGuard
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WinEH
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X86
[X86][AVX] getTargetConstantBitsFromNode - extract bits from X86ISD::SUBV_BROADCAST
2019-04-10 16:24:47 +00:00
XCore
…