Alex Bradbury 84f568a502 [RISCV] Codegen for conditional branches ... A good portion of this patch is the extra functions that needed to be implemented to support the test case. e.g. storeRegToStackSlot, loadRegFromStackSlot, eliminateFrameIndex. Setting ISD::BR_CC to Expand may appear non-obvious on an architecture with branch+cmp instructions. However, I found it much easier to deal with matching the expanded form. I had to change simm13_lsb0 and simm21_lsb0 to inherit from the Operand<OtherVT> class rather than Operand<i32> in order to keep tablegen happy. This isn't a big deal, but it does seem a shame to lose the uniformity across immediate types when there's not an obvious benefit (I'm hoping a tablegen expert will educate me on what I'm missing here!). Differential Revision: https://reviews.llvm.org/D29935 llvm-svn: 317690		2017-11-08 13:31:40 +00:00
..
AsmParser	[RISCV] RISCVAsmParser: early exit if RISCVOperand isn't immediate as expected	2017-10-19 16:22:51 +00:00
Disassembler	[RISCV] Prepare for the use of variable-sized register classes	2017-10-19 14:29:03 +00:00
InstPrinter	[RISCV] Add support for all RV32I instructions	2017-09-17 14:27:35 +00:00
MCTargetDesc	[RISCV] Prepare for the use of variable-sized register classes	2017-10-19 14:29:03 +00:00
TargetInfo	[RISCV] Add bare-bones RISC-V MCTargetDesc	2016-11-01 23:47:30 +00:00
CMakeLists.txt	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
LLVMBuild.txt	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCV.h	[RISCV] Codegen support for memory operations on global addresses	2017-11-08 13:24:21 +00:00
RISCV.td	[NFCI] Ensure TargetOpcode::* are compatible with guessInstructionProperties=0	2017-11-08 09:26:06 +00:00
RISCVAsmPrinter.cpp	[RISCV] Codegen support for memory operations on global addresses	2017-11-08 13:24:21 +00:00
RISCVCallingConv.td	[RISCV] Codegen for conditional branches	2017-11-08 13:31:40 +00:00
RISCVFrameLowering.cpp	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVFrameLowering.h	Move TargetFrameLowering.h to CodeGen where it's implemented	2017-11-03 22:32:11 +00:00
RISCVInstrFormats.td	[RISCV] Prepare for the use of variable-sized register classes	2017-10-19 14:29:03 +00:00
RISCVInstrInfo.cpp	[RISCV] Codegen for conditional branches	2017-11-08 13:31:40 +00:00
RISCVInstrInfo.h	[RISCV] Codegen for conditional branches	2017-11-08 13:31:40 +00:00
RISCVInstrInfo.td	[RISCV] Codegen for conditional branches	2017-11-08 13:31:40 +00:00
RISCVISelDAGToDAG.cpp	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVISelLowering.cpp	[RISCV] Codegen for conditional branches	2017-11-08 13:31:40 +00:00
RISCVISelLowering.h	[RISCV] Codegen support for memory operations on global addresses	2017-11-08 13:24:21 +00:00
RISCVMCInstLower.cpp	[RISCV] Codegen for conditional branches	2017-11-08 13:31:40 +00:00
RISCVRegisterInfo.cpp	[RISCV] Codegen for conditional branches	2017-11-08 13:31:40 +00:00
RISCVRegisterInfo.h	[RISCV] Codegen for conditional branches	2017-11-08 13:31:40 +00:00
RISCVRegisterInfo.td	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVSubtarget.cpp	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVSubtarget.h	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVTargetMachine.cpp	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVTargetMachine.h	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00