mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 03:23:01 +02:00
c2664c73ba
This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 llvm-svn: 316188
33 lines
1.0 KiB
CMake
33 lines
1.0 KiB
CMake
set(LLVM_TARGET_DEFINITIONS RISCV.td)
|
|
|
|
tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
|
|
tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
|
|
tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
|
|
tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
|
|
tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
|
|
tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
|
|
tablegen(LLVM RISCVGenCallingConv.inc -gen-callingconv)
|
|
tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
|
|
tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
|
|
tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
|
|
|
|
add_public_tablegen_target(RISCVCommonTableGen)
|
|
|
|
add_llvm_target(RISCVCodeGen
|
|
RISCVAsmPrinter.cpp
|
|
RISCVFrameLowering.cpp
|
|
RISCVInstrInfo.cpp
|
|
RISCVISelDAGToDAG.cpp
|
|
RISCVISelLowering.cpp
|
|
RISCVMCInstLower.cpp
|
|
RISCVRegisterInfo.cpp
|
|
RISCVSubtarget.cpp
|
|
RISCVTargetMachine.cpp
|
|
)
|
|
|
|
add_subdirectory(AsmParser)
|
|
add_subdirectory(Disassembler)
|
|
add_subdirectory(InstPrinter)
|
|
add_subdirectory(MCTargetDesc)
|
|
add_subdirectory(TargetInfo)
|