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f220e7cb76
We want to run the Machine Scheduler instead of the List Scheduler after RA. Checked with a performance run on a Power 9 machine with SPEC 2006 and while some benchmarks improved and others degraded the geomean was slightly improved with the Machine Scheduler. Differential Revision: https://reviews.llvm.org/D45265 llvm-svn: 336295
209 lines
5.5 KiB
LLVM
209 lines
5.5 KiB
LLVM
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel
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define signext i32 @testExpandISELToIfElse(i32 signext %i, i32 signext %j) {
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entry:
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%cmp = icmp sgt i32 %i, 0
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%add = add nsw i32 %i, 1
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%cond = select i1 %cmp, i32 %add, i32 %j
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ret i32 %cond
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; CHECK-LABEL: @testExpandISELToIfElse
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; CHECK: addi r5, r3, 1
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; CHECK-NEXT: cmpwi cr0, r3, 0
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; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
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; CHECK: ori r3, r4, 0
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; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
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; CHECK-NEXT: [[TRUE]]
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; CHECK-NEXT: addi r3, r5, 0
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; CHECK-NEXT: [[SUCCESSOR]]
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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}
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define signext i32 @testExpandISELToIf(i32 signext %i, i32 signext %j) {
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entry:
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%cmp = icmp sgt i32 %i, 0
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%cond = select i1 %cmp, i32 %j, i32 %i
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ret i32 %cond
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; CHECK-LABEL: @testExpandISELToIf
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; CHECK: cmpwi r3, 0
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; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
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; CHECK-NEXT: blr
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; CHECK-NEXT: [[TRUE]]
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; CHECK-NEXT: addi r3, r4, 0
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; CHECK-NEXT: blr
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}
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define signext i32 @testExpandISELToElse(i32 signext %i, i32 signext %j) {
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entry:
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%cmp = icmp sgt i32 %i, 0
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%cond = select i1 %cmp, i32 %i, i32 %j
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ret i32 %cond
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; CHECK-LABEL: @testExpandISELToElse
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; CHECK: cmpwi r3, 0
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; CHECK-NEXT: bclr 12, gt, 0
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; CHECK: ori r3, r4, 0
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; CHECK-NEXT: blr
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}
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define signext i32 @testExpandISELToNull(i32 signext %i, i32 signext %j) {
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entry:
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%cmp = icmp sgt i32 %i, 0
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%cond = select i1 %cmp, i32 %i, i32 %i
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ret i32 %cond
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; CHECK-LABEL: @testExpandISELToNull
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; CHECK-NOT: b {{.LBB[0-9]+}}
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; CHECK-NOT: bc
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; CHECK: blr
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}
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define signext i32 @testExpandISELsTo2ORIs2ADDIs
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(i32 signext %a, i32 signext %b, i32 signext %d,
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i32 signext %f, i32 signext %g) {
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entry:
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%cmp = icmp sgt i32 %g, 0
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%a.b = select i1 %cmp, i32 %g, i32 %b
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%d.f = select i1 %cmp, i32 %d, i32 %f
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%add = add nsw i32 %a.b, %d.f
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ret i32 %add
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; CHECK-LABEL: @testExpandISELsTo2ORIs2ADDIs
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; CHECK: cmpwi r7, 0
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; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
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; CHECK: ori r3, r4, 0
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; CHECK-NEXT: ori r4, r6, 0
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; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
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; CHECK-NEXT: [[TRUE]]
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; CHECK-NEXT: addi r3, r7, 0
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; CHECK-NEXT: addi r4, r5, 0
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; CHECK-NEXT: [[SUCCESSOR]]
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; CHECK-NEXT: add r3, r3, r4
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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}
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define signext i32 @testExpandISELsTo2ORIs1ADDI
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(i32 signext %a, i32 signext %b, i32 signext %d,
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i32 signext %f, i32 signext %g) {
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entry:
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%cmp = icmp sgt i32 %g, 0
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%a.b = select i1 %cmp, i32 %a, i32 %b
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%d.f = select i1 %cmp, i32 %d, i32 %f
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%add = add nsw i32 %a.b, %d.f
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ret i32 %add
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; CHECK-LABEL: @testExpandISELsTo2ORIs1ADDI
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; CHECK: cmpwi cr0, r7, 0
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; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
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; CHECK: ori r3, r4, 0
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; CHECK-NEXT: ori r4, r6, 0
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; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
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; CHECK-NEXT: [[TRUE]]
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; CHECK-NEXT: addi r4, r5, 0
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; CHECK-NEXT: [[SUCCESSOR]]
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; CHECK-NEXT: add r3, r3, r4
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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}
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define signext i32 @testExpandISELsTo1ORI1ADDI
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(i32 signext %a, i32 signext %b, i32 signext %d,
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i32 signext %f, i32 signext %g) {
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entry:
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%cmp = icmp sgt i32 %g, 0
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%a.b = select i1 %cmp, i32 %a, i32 %b
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%d.f = select i1 %cmp, i32 %d, i32 %f
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%add1 = add nsw i32 %a.b, %d.f
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%add2 = add nsw i32 %a, %add1
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ret i32 %add2
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; CHECK-LABEL: @testExpandISELsTo1ORI1ADDI
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; CHECK: cmpwi cr0, r7, 0
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; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
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; CHECK: ori r5, r6, 0
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; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
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; CHECK-NEXT: [[TRUE]]
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; CHECK-NEXT: addi r4, r3, 0
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; CHECK-NEXT: [[SUCCESSOR]]
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; CHECK-NEXT: add r4, r4, r5
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; CHECK-NEXT: add r3, r3, r4
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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}
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define signext i32 @testExpandISELsTo0ORI2ADDIs
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(i32 signext %a, i32 signext %b, i32 signext %d,
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i32 signext %f, i32 signext %g) {
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entry:
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%cmp = icmp sgt i32 %g, 0
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%a.b = select i1 %cmp, i32 %a, i32 %b
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%d.f = select i1 %cmp, i32 %d, i32 %f
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%add1 = add nsw i32 %a.b, %d.f
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%add2 = add nsw i32 %a, %add1
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%sub1 = sub nsw i32 %add2, %d
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ret i32 %sub1
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; CHECK-LABEL: @testExpandISELsTo0ORI2ADDIs
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; CHECK: cmpwi cr0, r7, 0
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; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
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; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
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; CHECK-NEXT: [[TRUE]]
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; CHECK-NEXT: addi r4, r3, 0
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; CHECK-NEXT: addi r6, r5, 0
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; CHECK-NEXT: [[SUCCESSOR]]
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; CHECK-NEXT: add r4, r4, r6
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; CHECK-NEXT: add r3, r3, r4
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; CHECK-NEXT: subf r3, r5, r3
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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}
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@b = common local_unnamed_addr global i32 0, align 4
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@a = common local_unnamed_addr global i32 0, align 4
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; Function Attrs: norecurse nounwind readonly
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define signext i32 @testComplexISEL() #0 {
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entry:
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%0 = load i32, i32* @b, align 4, !tbaa !1
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%tobool = icmp eq i32 %0, 0
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br i1 %tobool, label %if.end, label %cleanup
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if.end:
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%1 = load i32, i32* @a, align 4, !tbaa !1
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%conv = sext i32 %1 to i64
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%2 = inttoptr i64 %conv to i32 (...)*
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%cmp = icmp eq i32 (...)* %2, bitcast (i32 ()* @testComplexISEL to i32 (...)*)
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%conv3 = zext i1 %cmp to i32
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br label %cleanup
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cleanup:
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%retval.0 = phi i32 [ %conv3, %if.end ], [ 1, %entry ]
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ret i32 %retval.0
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; CHECK-LABEL: @testComplexISEL
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; CHECK: cmplwi r3, 0
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; CHECK: li r3, 1
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; CHECK: beq cr0, [[TGT:.LBB[0-9_]+]]
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; CHECK: clrldi r3, r3, 32
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; CHECK: blr
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; CHECK: [[TGT]]
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; CHECK: xor [[XOR:r[0-9]+]]
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; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]]
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; CHECK: rldicl [[SH:r[0-9]+]], [[CZ]], 58, 63
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}
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!1 = !{!2, !2, i64 0}
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!2 = !{!"int", !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C/C++ TBAA"}
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