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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
30 lines
650 B
YAML
30 lines
650 B
YAML
# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
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# This test ensures that the MIR parser parses the cfi offset operands
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# correctly.
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--- |
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define void @test() {
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entry:
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%tmp = alloca [4168 x i8], align 4
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ret void
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}
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...
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---
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name: test
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tracksRegLiveness: true
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frameInfo:
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stackSize: 4040
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stack:
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- { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
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body: |
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bb.0.entry:
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$rsp = SUB64ri32 $rsp, 4040, implicit-def dead $eflags
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; CHECK: CFI_INSTRUCTION def_cfa_offset 4048
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CFI_INSTRUCTION def_cfa_offset 4048
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$rsp = ADD64ri32 $rsp, 4040, implicit-def dead $eflags
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RETQ
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...
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