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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
31 lines
930 B
YAML
31 lines
930 B
YAML
# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
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--- |
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define void @memory_alignment(<8 x float>* %vec) {
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entry:
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%v = load <8 x float>, <8 x float>* %vec
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%v2 = insertelement <8 x float> %v, float 0.0, i32 4
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store <8 x float> %v2, <8 x float>* %vec
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ret void
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}
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...
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---
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name: memory_alignment
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tracksRegLiveness: true
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liveins:
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- { reg: '$rdi' }
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body: |
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bb.0.entry:
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liveins: $rdi
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; CHECK: [[@LINE+1]]:71: expected an integer literal after 'align'
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$xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align -32)
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$xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
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$xmm2 = FsFLD0SS
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$xmm1 = MOVSSrr killed $xmm1, killed $xmm2
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MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store 16 into %ir.vec, align 32)
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MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store 16 into %ir.vec + 16, align 32)
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RETQ
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...
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