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llvm-mirror/test/CodeGen/ARM/2012-08-30-select.ll
Nadav Rotem d1815a0763 Not all targets have efficient ISel code generation for select instructions.
For example, the ARM target does not have efficient ISel handling for vector
selects with scalar conditions. This patch adds a TLI hook which allows the
different targets to report which selects are supported well and which selects
should be converted to CF duting codegen prepare.

llvm-svn: 163093
2012-09-02 12:10:19 +00:00

19 lines
493 B
LLVM

; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
; rdar://12201387
;CHECK: select_s_v_v
;CHECK: it ne
;CHECK-NEXT: vmovne.i32
;CHECK: bx
define <16 x i8> @select_s_v_v(i32 %avail, i8* %bar) {
entry:
%vld1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %bar, i32 1)
%and = and i32 %avail, 1
%tobool = icmp eq i32 %and, 0
%vld1. = select i1 %tobool, <16 x i8> %vld1, <16 x i8> zeroinitializer
ret <16 x i8> %vld1.
}
declare <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* , i32 )