mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 19:23:23 +01:00
6383fd81a8
Currently PowerPC backend emits code like this: r3 = li 0 std r3, 264(r1) r3 = li 0 std r3, 272(r1) This patch fixes that and other cases where a register already contains a value that is loaded so we will get: r3 = li 0 std r3, 264(r1) std r3, 272(r1) Differential Revision: https://reviews.llvm.org/D64220 llvm-svn: 366840
349 lines
8.9 KiB
YAML
349 lines
8.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -run-pass ppc-pre-emit-peephole %s -o - | FileCheck %s
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---
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name: t1
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x1
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; CHECK-LABEL: name: t1
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; CHECK: liveins: $x1
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; CHECK: renamable $x3 = LI8 0
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; CHECK: STD renamable $x3, 16, $x1
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; CHECK: STD killed renamable $x3, 8, $x1
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; CHECK: BLR8 implicit $lr8, implicit $rm
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renamable $x3 = LI8 0
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STD killed renamable $x3, 16, $x1
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renamable $x3 = LI8 0
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STD killed renamable $x3, 8, $x1
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: t2
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x1
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; CHECK-LABEL: name: t2
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; CHECK: liveins: $x1
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; CHECK: renamable $x3 = LI8 0
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; CHECK: STD renamable $x3, 32, $x1
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; CHECK: STD renamable $x3, 24, $x1
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; CHECK: STD renamable $x3, 16, $x1
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; CHECK: STD killed renamable $x3, 8, $x1
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; CHECK: BLR8 implicit $lr8, implicit $rm
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renamable $x3 = LI8 0
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STD killed renamable $x3, 32, $x1
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renamable $x3 = LI8 0
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STD killed renamable $x3, 24, $x1
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renamable $x3 = LI8 0
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STD killed renamable $x3, 16, $x1
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renamable $x3 = LI8 0
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STD killed renamable $x3, 8, $x1
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: t3
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x1
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; CHECK-LABEL: name: t3
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; CHECK: liveins: $x1
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; CHECK: renamable $x3 = LI8 0
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; CHECK: STD renamable $x3, 32, $x1
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; CHECK: STD renamable $x3, 24, $x1
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; CHECK: BLR8 implicit $lr8, implicit $rm
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renamable $x3 = LI8 0
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STD killed renamable $x3, 32, $x1
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renamable $x3 = LI8 0
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STD renamable $x3, 24, $x1
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: t4
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x1
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; CHECK-LABEL: name: t4
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; CHECK: liveins: $x1
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; CHECK: renamable $x3 = LI8 0
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; CHECK: STD renamable $x3, 16, $x1
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; CHECK: renamable $x4 = ADDI8 renamable $x3, 8
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; CHECK: STD killed renamable $x3, 8, $x1
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; CHECK: BLR8 implicit $lr8, implicit $rm
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renamable $x3 = LI8 0
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STD killed renamable $x3, 16, $x1
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renamable $x3 = LI8 0
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renamable $x4 = ADDI8 killed renamable $x3, 8
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renamable $x3 = LI8 0
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STD killed renamable $x3, 8, $x1
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: t5
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x1
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; CHECK-LABEL: name: t5
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; CHECK: liveins: $x1
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; CHECK: renamable $r3 = LI 0
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; CHECK: STW renamable $r3, 16, $x1
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; CHECK: STW killed renamable $r3, 12, $x1
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; CHECK: renamable $r3 = LI 1
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; CHECK: BLR8 implicit $lr8, implicit $rm
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renamable $r3 = LI 0
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STW killed renamable $r3, 16, $x1
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renamable $r3 = LI 0
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STW killed renamable $r3, 12, $x1
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renamable $r3 = LI 1
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: t6
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x1
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; CHECK-LABEL: name: t6
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; CHECK: liveins: $x1
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; CHECK: renamable $x3 = LI8 0
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; CHECK: renamable $x4 = LI8 1
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; CHECK: STD renamable $x3, 32, $x1
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; CHECK: STD renamable $x4, 24, $x1
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; CHECK: STD killed renamable $x3, 16, $x1
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; CHECK: STD killed renamable $x4, 8, $x1
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; CHECK: BLR8 implicit $lr8, implicit $rm
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renamable $x3 = LI8 0
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renamable $x4 = LI8 1
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STD killed renamable $x3, 32, $x1
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STD killed renamable $x4, 24, $x1
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renamable $x3 = LI8 0
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renamable $x4 = LI8 1
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STD killed renamable $x3, 16, $x1
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STD killed renamable $x4, 8, $x1
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: t7
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x1, $x4
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; CHECK-LABEL: name: t7
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; CHECK: liveins: $x1, $x4
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; CHECK: renamable $x3 = LI8 0
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; CHECK: STD killed renamable $x3, 32, $x1
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; CHECK: renamable $x3 = ADDI8 $x4, 6
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; CHECK: BLR8 implicit $lr8, implicit $rm
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renamable $x3 = LI8 0
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STD killed renamable $x3, 32, $x1
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renamable $x3 = ADDI8 $x4, 6
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: t8
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x1
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; CHECK-LABEL: name: t8
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; CHECK: liveins: $x1
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; CHECK: renamable $x3 = LI8 0
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; CHECK: STD renamable $x3, 32, $x1
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; CHECK: BLR8 implicit $lr8, implicit $rm
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renamable $x3 = LI8 0
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STD killed renamable $x3, 32, $x1
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renamable $x3 = LI8 0
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: t9
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: t9
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: liveins: $x3
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; CHECK: renamable $r4 = LI 0, implicit-def $x4
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; CHECK: renamable $x24 = RLDICL renamable $x4, 0, 32
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; CHECK: renamable $cr0 = CMPLDI renamable $x3, 0
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; CHECK: BCC 68, killed renamable $cr0, %bb.1
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; CHECK: B %bb.2
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; CHECK: bb.1:
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; CHECK: liveins: $r4, $x1
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; CHECK: STW killed renamable $r4, 16, $x1
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; CHECK: BLR8 implicit $lr8, implicit $rm
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; CHECK: bb.2:
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; CHECK: liveins: $r4, $x1
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; CHECK: STW killed renamable $r4, 32, $x1
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; CHECK: BLR8 implicit $lr8, implicit $rm
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bb.0.entry:
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liveins: $x3
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successors: %bb.8, %bb.7
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renamable $r4 = LI 0, implicit-def $x4
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renamable $x24 = RLDICL killed renamable $x4, 0 , 32
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renamable $cr0 = CMPLDI renamable $x3, 0
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renamable $r4 = LI 0
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BCC 68, killed renamable $cr0, %bb.7
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B %bb.8
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bb.7:
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liveins: $r4, $x1
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STW killed renamable $r4, 16, $x1
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BLR8 implicit $lr8, implicit $rm
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bb.8:
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liveins: $r4, $x1
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STW killed renamable $r4, 32, $x1
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: t10
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x1
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; CHECK-LABEL: name: t10
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; CHECK: liveins: $x1
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; CHECK: renamable $x3 = LI8 24
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; CHECK: STD killed renamable $x3, 16, $x1
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; CHECK: renamable $r3 = LI 0
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; CHECK: STW killed renamable $r3, 26, $x1
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; CHECK: BLR8 implicit $lr8, implicit $rm
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renamable $x3 = LI8 24
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STD killed renamable $x3, 16, $x1
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renamable $r3 = LI 0
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STW killed renamable $r3, 26, $x1
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: LIS8
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x1
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; CHECK-LABEL: name: LIS8
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; CHECK: liveins: $x1
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; CHECK: renamable $x3 = LIS8 0
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; CHECK: STD renamable $x3, 16, $x1
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; CHECK: STD killed renamable $x3, 8, $x1
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; CHECK: BLR8 implicit $lr8, implicit $rm
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renamable $x3 = LIS8 0
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STD killed renamable $x3, 16, $x1
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renamable $x3 = LIS8 0
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STD killed renamable $x3, 8, $x1
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: LIS
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x1
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; CHECK-LABEL: name: LIS
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; CHECK: liveins: $x1
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; CHECK: renamable $r3 = LIS 0
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; CHECK: STW renamable $r3, 16, $x1
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; CHECK: STW killed renamable $r3, 12, $x1
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; CHECK: BLR8 implicit $lr8, implicit $rm
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renamable $r3 = LIS 0
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STW killed renamable $r3, 16, $x1
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renamable $r3 = LIS 0
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STW killed renamable $r3, 12, $x1
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: modify_and_kill_the_reg_in_the_same_inst
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: modify_and_kill_the_reg_in_the_same_inst
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; CHECK: renamable $x6 = LI8 1
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; CHECK: renamable $x6 = RLDICR killed renamable $x6, 44, 19
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; CHECK: BLR8 implicit $lr8, implicit $rm
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renamable $x6 = LI8 1
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renamable $x6 = RLDICR killed renamable $x6, 44, 19
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: dead_load_immediate_followed_by_a_redundancy
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x1
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; CHECK-LABEL: name: dead_load_immediate_followed_by_a_redundancy
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; CHECK: liveins: $x1
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; CHECK: renamable $r3 = LI 128
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; CHECK: renamable $x4 = ADDI8 $x1, -128
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; CHECK: renamable $x5 = ADDI8 $x1, -128
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; CHECK: STW killed renamable $r3, 16, $x4
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; CHECK: BLR8 implicit $lr8, implicit $rm
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dead renamable $r3 = LI 128
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renamable $x4 = ADDI8 $x1, -128
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dead renamable $r3 = LI 128
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renamable $x5 = ADDI8 $x1, -128
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renamable $r3 = LI 128
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STW killed renamable $r3, 16, $x4
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BLR8 implicit $lr8, implicit $rm
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...
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