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3f9ad6b478
This re-commits everything that was pulled in r314244. The transformation is off by default (patch to enable it to follow). The code is refactored to have a single entry-point and provide fine-grained control over patterns that it selects. This patch also fixes the bugs in the original code. Everything that failed with the original patch has been re-tested with this patch (with the transformation turned on). So the patch to turn this on is soon to follow. Differential Revision: https://reviews.llvm.org/D38575 llvm-svn: 319434
116 lines
3.2 KiB
LLVM
116 lines
3.2 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = common local_unnamed_addr global i64 0, align 8
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llleull(i64 %a, i64 %b) {
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entry:
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%cmp = icmp ule i64 %a, %b
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%conv1 = zext i1 %cmp to i64
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ret i64 %conv1
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; CHECK-LABEL: test_llleull:
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; CHECK: subfc {{r[0-9]+}}, r3, r4
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; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r3, r3
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; CHECK-NEXT: addi r3, [[REG1]], 1
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llleull_sext(i64 %a, i64 %b) {
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entry:
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%cmp = icmp ule i64 %a, %b
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%conv1 = sext i1 %cmp to i64
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ret i64 %conv1
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; CHECK-LABEL: @test_llleull_sext
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; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
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; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
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; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llleull_z(i64 %a) {
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entry:
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%cmp = icmp ule i64 %a, 0
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%conv1 = zext i1 %cmp to i64
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ret i64 %conv1
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; CHECK-LABEL: test_llleull_z
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; CHECK: cntlzd [[REG1:r[0-9]+]], r3
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; CHECK-NEXT: rldicl r3, [[REG1]], 58, 63
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llleull_sext_z(i64 %a) {
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entry:
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%cmp = icmp ule i64 %a, 0
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%conv1 = sext i1 %cmp to i64
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ret i64 %conv1
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; CHECK-LABEL: @test_llleull_sext_z
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; CHECK: addic [[REG1:r[0-9]+]], r3, -1
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; CHECK: subfe r3, [[REG1]]
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_llleull_store(i64 %a, i64 %b) {
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entry:
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%cmp = icmp ule i64 %a, %b
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob
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ret void
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; CHECK-LABEL: test_llleull_store:
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; CHECK: subfc {{r[0-9]+}}, r3, r4
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; CHECK: subfe [[REG1:r[0-9]+]], r3, r3
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; CHECK: addi r3, [[REG1]], 1
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_llleull_sext_store(i64 %a, i64 %b) {
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entry:
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%cmp = icmp ule i64 %a, %b
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob
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ret void
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; CHECK-LABEL: @test_llleull_sext_store
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; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
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; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
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; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
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; CHECK: std [[REG3]]
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_llleull_z_store(i64 %a) {
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entry:
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%cmp = icmp ule i64 %a, 0
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob
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ret void
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; CHECK-LABEL: test_llleull_z_store:
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; CHECK: cntlzd [[REG1:r[0-9]+]], r3
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; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 58, 63
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_llleull_sext_z_store(i64 %a) {
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entry:
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%cmp = icmp ule i64 %a, 0
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob
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ret void
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; CHECK-LABEL: @test_llleull_sext_z_store
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; CHECK: addic [[REG1:r[0-9]+]], r3, -1
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; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
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; CHECK: std [[REG2]]
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; CHECK: blr
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}
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