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45f5d3d85c
The DAG combiner logic to simplify AND masks in shift counts is invalid. While it is true that the SystemZ shift instructions ignore all but the low 6 bits of the shift count, it is still invalid to simplify the AND masks while the DAG still uses the standard shift operators (which are *not* defined to match the SystemZ instruction behavior). Instead, this patch performs equivalent operations during instruction selection. For completely removing the AND, this now happens via additional DAG match patterns implemented by a multi-alternative PatFrags. For simplifying a 32-bit AND to a 16-bit AND, the existing DAG patterns were already mostly OK, they just needed an output XForm to actually truncate the immediate value. Unfortunately, the latter change also exposed a bug in TableGen: it seems XForms are currently only handled correctly for direct operands of the outermost operation node. This patch also fixes that bug by simply recurring through the whole pattern. This should be NFC for all other targets. Differential Revision: https://reviews.llvm.org/D50096 llvm-svn: 338521
119 lines
2.8 KiB
LLVM
119 lines
2.8 KiB
LLVM
; Test removal of AND operations that don't affect last 6 bits of shift amount
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; operand.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test that AND is not removed when some lower 6 bits are not set.
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define i32 @f1(i32 %a, i32 %sh) {
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; CHECK-LABEL: f1:
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; CHECK: nil{{[lf]}} %r3, 31
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; CHECK: sll %r2, 0(%r3)
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%and = and i32 %sh, 31
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%shift = shl i32 %a, %and
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ret i32 %shift
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}
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; Test removal of AND mask with only bottom 6 bits set.
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define i32 @f2(i32 %a, i32 %sh) {
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; CHECK-LABEL: f2:
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; CHECK-NOT: nil{{[lf]}} %r3, 63
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; CHECK: sll %r2, 0(%r3)
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%and = and i32 %sh, 63
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%shift = shl i32 %a, %and
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ret i32 %shift
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}
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; Test removal of AND mask including but not limited to bottom 6 bits.
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define i32 @f3(i32 %a, i32 %sh) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: nil{{[lf]}} %r3, 255
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; CHECK: sll %r2, 0(%r3)
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%and = and i32 %sh, 255
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%shift = shl i32 %a, %and
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ret i32 %shift
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}
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; Test removal of AND mask from SRA.
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define i32 @f4(i32 %a, i32 %sh) {
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; CHECK-LABEL: f4:
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; CHECK-NOT: nil{{[lf]}} %r3, 63
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; CHECK: sra %r2, 0(%r3)
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%and = and i32 %sh, 63
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%shift = ashr i32 %a, %and
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ret i32 %shift
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}
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; Test removal of AND mask from SRL.
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define i32 @f5(i32 %a, i32 %sh) {
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; CHECK-LABEL: f5:
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; CHECK-NOT: nil{{[lf]}} %r3, 63
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; CHECK: srl %r2, 0(%r3)
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%and = and i32 %sh, 63
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%shift = lshr i32 %a, %and
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ret i32 %shift
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}
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; Test removal of AND mask from SLLG.
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define i64 @f6(i64 %a, i64 %sh) {
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; CHECK-LABEL: f6:
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; CHECK-NOT: nil{{[lf]}} %r3, 63
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; CHECK: sllg %r2, %r2, 0(%r3)
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%and = and i64 %sh, 63
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%shift = shl i64 %a, %and
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ret i64 %shift
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}
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; Test removal of AND mask from SRAG.
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define i64 @f7(i64 %a, i64 %sh) {
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; CHECK-LABEL: f7:
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; CHECK-NOT: nil{{[lf]}} %r3, 63
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; CHECK: srag %r2, %r2, 0(%r3)
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%and = and i64 %sh, 63
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%shift = ashr i64 %a, %and
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ret i64 %shift
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}
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; Test removal of AND mask from SRLG.
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define i64 @f8(i64 %a, i64 %sh) {
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; CHECK-LABEL: f8:
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; CHECK-NOT: nil{{[lf]}} %r3, 63
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; CHECK: srlg %r2, %r2, 0(%r3)
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%and = and i64 %sh, 63
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%shift = lshr i64 %a, %and
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ret i64 %shift
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}
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; Test that AND with two register operands is not affected.
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define i32 @f9(i32 %a, i32 %b, i32 %sh) {
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; CHECK-LABEL: f9:
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; CHECK: nr %r3, %r4
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; CHECK: sll %r2, 0(%r3)
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%and = and i32 %sh, %b
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%shift = shl i32 %a, %and
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ret i32 %shift
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}
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; Test that AND is not entirely removed if the result is reused.
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define i32 @f10(i32 %a, i32 %sh) {
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; CHECK-LABEL: f10:
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; CHECK: sll %r2, 0(%r3)
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; CHECK: nil{{[lf]}} %r3, 63
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; CHECK: ar %r2, %r3
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%and = and i32 %sh, 63
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%shift = shl i32 %a, %and
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%reuse = add i32 %and, %shift
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ret i32 %reuse
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}
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; Test that AND is not removed for i128 (which calls __ashlti3)
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define i128 @f11(i128 %a, i32 %sh) {
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; CHECK-LABEL: f11:
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; CHECK: risbg %r4, %r4, 57, 191, 0
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; CHECK: brasl %r14, __ashlti3@PLT
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%and = and i32 %sh, 127
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%ext = zext i32 %and to i128
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%shift = shl i128 %a, %ext
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ret i128 %shift
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}
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