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262321d1ff
This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"
For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"
Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.
Differential Revision: https://reviews.llvm.org/D38851
llvm-svn: 316101
45 lines
1.8 KiB
LLVM
45 lines
1.8 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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;
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; Check that this testcase doesn't crash.
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; CHECK: vadd
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target triple = "hexagon"
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define void @fred() #0 {
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b0:
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br label %b1
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b1: ; preds = %b7, %b0
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%v2 = phi i32 [ 0, %b0 ], [ %v16, %b7 ]
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%v3 = phi <32 x i32> [ undef, %b0 ], [ %v15, %b7 ]
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%v4 = icmp slt i32 %v2, undef
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br i1 %v4, label %b5, label %b7
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b5: ; preds = %b1
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%v6 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v3, <32 x i32> undef)
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br label %b7
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b7: ; preds = %b5, %b1
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%v8 = phi <32 x i32> [ %v6, %b5 ], [ %v3, %b1 ]
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%v9 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v8, <32 x i32> undef)
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%v10 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v9, <32 x i32> undef)
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%v11 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v10, <32 x i32> undef)
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%v12 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v11, <32 x i32> undef)
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%v13 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v12, <32 x i32> zeroinitializer)
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%v14 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v13, <32 x i32> undef)
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%v15 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v14, <32 x i32> undef)
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%v16 = add nsw i32 %v2, 8
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%v17 = icmp eq i32 %v16, 64
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br i1 %v17, label %b18, label %b1
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b18: ; preds = %b7
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tail call void @f0() #0
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ret void
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}
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declare <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32>, <32 x i32>) #1
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declare void @f0() #0
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
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attributes #1 = { nounwind readnone }
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