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69 lines
2.7 KiB
LLVM
69 lines
2.7 KiB
LLVM
; RUN: llc -O2 -march=hexagon < %s
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; REQUIRES: asserts
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; Test that the final instruction ordering code does not result in infinite
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; recursion (a segmentation fault). The problem is that the order heuristics
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; did not properly take into account the stage in which an instruction is
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; scheduled.
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%0 = type { %1, %4, %9, %28 }
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%1 = type { i8, [32 x %2] }
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%2 = type { i8, %3, i8, i8, i16, i8, [20 x i16], [20 x i16] }
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%3 = type { i16, i8 }
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%4 = type { i8, [64 x %5], [64 x %5*] }
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%5 = type { i8, i8, i8*, %6 }
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%6 = type { %7 }
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%7 = type { i8*, %3, i8, i8, i8, i8, i16, i8, i8, i8, i16, i32, i8, [3 x i8], [3 x i16], i16, i8, i16, i8, %8, i16, i8, i16 }
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%8 = type { i8, i8 }
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%9 = type { i8, i8, %10*, i8, [8 x %7*], i8, i8, i8, i8, i8, %7*, i8, %7*, i8, i8, i8, i8, i8, i8, i8, i8, i32, i8, i32, i32, i32, i32, i32, i32, i32, i8, i8, i16, i8, void (i8)*, i8, i8, i8, i8, i8, i8 }
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%10 = type { i8, i8, i8, i8, i8, %11, %12, %13, %14 }
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%11 = type { i8, i16, i16 }
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%12 = type { i8, i16, i8* }
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%13 = type { i8, i16 }
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%14 = type { %15, %20, %25 }
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%15 = type { i8, i8, %16, i8, [18 x %17] }
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%16 = type { i8, i16, i16 }
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%17 = type { i8, i8, [10 x %3], [10 x i16], [10 x i16], [10 x i8], %18* }
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%18 = type { %19, i16, i16, %19, i16 }
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%19 = type { i16, i16, i16, i8 }
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%20 = type { i8, i8, %21 }
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%21 = type { i8*, %22, %23 }
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%22 = type { %3, i8, i8, i16, i16, i16, i8, i16 }
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%23 = type { [2 x %24], [4 x i8] }
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%24 = type { i8, %3, i16, i16, i16, i16, %18* }
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%25 = type { i8, i8, [8 x %26] }
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%26 = type { i8*, %27, %24 }
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%27 = type { %3, i8, i16, i16, i16 }
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%28 = type { [2 x %29], [2 x i16], i8, i8*, i16, i8, i8, %31*, %32*, %33*, %33*, [3 x %34*], i8, [2 x i8], i8, i8, [2 x i8], [2 x i8], [3 x i8] }
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%29 = type <{ %30, i8, [1000 x i8] }>
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%30 = type { i16, i16, [2 x i32] }
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%31 = type <{ i8, i8, i16, i8 }>
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%32 = type <{ i16, i16, i8, i16 }>
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%33 = type <{ i8, i8, i16, i16, i16, i8, i16, i16 }>
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%34 = type <{ i8, i8, i16, i16, i8, i16, i8, i8, i32, i16, i16, i16 }>
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@g0 = external global [2 x %0], align 8
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; Function Attrs: nounwind ssp
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define void @f0() #0 {
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b0:
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br label %b1
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b1: ; preds = %b1, %b0
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%v0 = phi i32 [ 0, %b0 ], [ %v5, %b1 ]
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%v1 = getelementptr inbounds [2 x %0], [2 x %0]* @g0, i32 0, i32 undef, i32 1, i32 1, i32 %v0
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%v2 = getelementptr inbounds [2 x %0], [2 x %0]* @g0, i32 0, i32 undef, i32 1, i32 2, i32 %v0
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store %5* %v1, %5** %v2, align 4
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%v3 = getelementptr inbounds [2 x %0], [2 x %0]* @g0, i32 0, i32 undef, i32 1, i32 1, i32 %v0, i32 3
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%v4 = bitcast %6* %v3 to %5**
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store %5* %v1, %5** %v4, align 4
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%v5 = add nuw nsw i32 %v0, 1
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%v6 = icmp eq i32 %v5, 64
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br i1 %v6, label %b2, label %b1
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b2: ; preds = %b1
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ret void
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}
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attributes #0 = { nounwind ssp "target-cpu"="hexagonv55" }
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