mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 19:52:54 +01:00
c28d8cf19b
This commit removes the artificial types <512 x i1> and <1024 x i1>
from HVX intrinsics, and makes v512i1 and v1024i1 no longer legal on
Hexagon.
It may cause existing bitcode files to become invalid.
* Converting between vector predicates and vector registers must be
done explicitly via vandvrt/vandqrt instructions (their intrinsics),
i.e. (for 64-byte mode):
%Q = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %V, i32 -1)
%V = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %Q, i32 -1)
The conversion intrinsics are:
declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32)
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)
declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32)
They are all pure.
* Vector predicate values cannot be loaded/stored directly. This directly
reflects the architecture restriction. Loading and storing or vector
predicates must be done indirectly via vector registers and explicit
conversions via vandvrt/vandqrt instructions.
33 lines
968 B
LLVM
33 lines
968 B
LLVM
; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s
|
|
; CHECK: q{{[0-3]}} = vsetq(r{{[0-9]+}})
|
|
|
|
target triple = "hexagon"
|
|
|
|
; Function Attrs: nounwind
|
|
define void @f0(i32 %a0, <16 x i32> %a1) #0 {
|
|
b0:
|
|
%v0 = alloca i32, align 4
|
|
%v1 = alloca <16 x i32>, align 64
|
|
%v2 = alloca <16 x i32>, align 64
|
|
store i32 %a0, i32* %v0, align 4
|
|
store <16 x i32> %a1, <16 x i32>* %v1, align 64
|
|
%v3 = load i32, i32* %v0, align 4
|
|
%v4 = tail call <64 x i1> asm sideeffect " $0 = vsetq($1);\0A", "=q,r"(i32 %v3) #1, !srcloc !0
|
|
%v5 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v4, i32 -1)
|
|
store <16 x i32> %v5, <16 x i32>* %v2, align 64
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: nounwind
|
|
define i32 @f1() #0 {
|
|
b0:
|
|
ret i32 0
|
|
}
|
|
|
|
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) #1
|
|
|
|
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
|
|
attributes #1 = { nounwind readnone }
|
|
|
|
!0 = !{i32 222}
|