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llvm-mirror/lib/CodeGen/SelectionDAG
2011-06-24 23:02:22 +00:00
..
CMakeLists.txt
DAGCombiner.cpp Replace the existing forms of ConstantArray::get() with a single form 2011-06-22 09:24:39 +00:00
FastISel.cpp Handle debug info for i128 constants. 2011-06-24 20:46:11 +00:00
FunctionLoweringInfo.cpp Add a parameter to CCState so that it can access the MachineFunction. 2011-06-08 23:55:35 +00:00
InstrEmitter.cpp Handle debug info for i128 constants. 2011-06-24 20:46:11 +00:00
InstrEmitter.h
LegalizeDAG.cpp Add a testcase for checking the integer-promotion of many different vector 2011-06-14 08:11:52 +00:00
LegalizeFloatTypes.cpp Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. 2011-02-25 21:41:48 +00:00
LegalizeIntegerTypes.cpp Fix PromoteIntRes_TRUNCATE: Add support for cases where the 2011-06-20 07:15:58 +00:00
LegalizeTypes.cpp Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer use 2011-06-01 19:47:10 +00:00
LegalizeTypes.h Lower multiply with overflow checking to __mulo<mode> 2011-06-17 20:41:29 +00:00
LegalizeTypesGeneric.cpp Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer use 2011-06-01 19:47:10 +00:00
LegalizeVectorOps.cpp Add support for legalizing UINT_TO_FP of vectors on platforms which do 2011-03-19 13:09:10 +00:00
LegalizeVectorTypes.cpp Fix a bug in FindMemType. When widening vector loads, use a wider memory type 2011-06-13 18:13:24 +00:00
Makefile
ScheduleDAGFast.cpp Re-commit 127368 and 127371. They are exonerated. 2011-03-10 00:16:32 +00:00
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp Fix some trailing issues from my introduction of MVT::untyped and its use for REGISTER_SEQUENCE. 2011-06-21 22:54:23 +00:00
ScheduleDAGSDNodes.cpp The scheduler needs to be aware on the existence of untyped nodes when it performs type propagation for EXTRACT_SUBREG. 2011-06-24 23:02:22 +00:00
ScheduleDAGSDNodes.h Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match. 2011-06-15 23:35:18 +00:00
SDNodeDbgValue.h Do not lose debug info of an inlined function argument even if the argument is only used through GEPs. 2011-02-18 22:43:42 +00:00
SDNodeOrdering.h
SelectionDAG.cpp Don't allocate empty read-only SmallVectors during SelectionDAG deallocation. 2011-06-18 13:13:44 +00:00
SelectionDAGBuilder.cpp When promoting the vector elements in CopyToParts, use vector trunc 2011-06-19 08:49:38 +00:00
SelectionDAGBuilder.h Introduce MachineBranchProbabilityInfo class, which has similar API to 2011-06-16 20:22:37 +00:00
SelectionDAGISel.cpp Introduce MachineBranchProbabilityInfo class, which has similar API to 2011-06-16 20:22:37 +00:00
SelectionDAGPrinter.cpp Pass the graph to the DOTGraphTraits.getEdgeAttributes(). 2011-02-27 04:11:03 +00:00
TargetLowering.cpp Lower multiply with overflow checking to __mulo<mode> 2011-06-17 20:41:29 +00:00
TargetSelectionDAGInfo.cpp