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llvm-mirror/lib/Target/Hexagon
Shengchen Kan 88597bc560 [MC][Bugfix] Remove redundant parameter for relaxInstruction
Summary:
Before this patch, `relaxInstruction` takes three arguments, the first
argument refers to the instruction before relaxation and the third
argument is the output instruction after relaxation. There are two quite
strange things:
  1) The first argument's type is `const MCInst &`, the third
  argument's type is `MCInst &`, but they may be aliased to the same
  variable
  2) The backends of ARM, AMDGPU, RISC-V, Hexagon assume that the third
  argument is a fresh uninitialized `MCInst` even if `relaxInstruction`
  may be called like `relaxInstruction(Relaxed, STI, Relaxed)` in a
  loop.

In this patch, we drop the thrid argument, and let `relaxInstruction`
directly modify the given instruction. Also, this patch fixes the bug https://bugs.llvm.org/show_bug.cgi?id=45580, which is introduced by D77851, and
breaks the assumption of ARM, AMDGPU, RISC-V, Hexagon.

Reviewers: Razer6, MaskRay, jyknight, asb, luismarques, enderby, rtaylor, colinl, bcain

Reviewed By: Razer6, MaskRay, bcain

Subscribers: bcain, nickdesaulniers, nathanchance, wuzish, annita.zhang, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, tpr, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78364
2020-04-21 11:06:55 +08:00
..
AsmParser [MCStreamer] De-capitalize EmitValue EmitIntValue{,InHex} 2020-02-14 23:08:40 -08:00
Disassembler [Hexagon] v67+ HVX register pairs should support either direction 2020-02-14 12:43:43 -06:00
MCTargetDesc [MC][Bugfix] Remove redundant parameter for relaxInstruction 2020-04-21 11:06:55 +08:00
TargetInfo
BitTracker.cpp
BitTracker.h
CMakeLists.txt Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
Hexagon.h
Hexagon.td [TableGen] Support combining AssemblerPredicates with ORs 2020-03-13 17:13:51 +00:00
HexagonArch.h
HexagonAsmPrinter.cpp [MCStreamer] De-capitalize EmitValue EmitIntValue{,InHex} 2020-02-14 23:08:40 -08:00
HexagonAsmPrinter.h [AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI* 2020-02-13 22:08:55 -08:00
HexagonBitSimplify.cpp [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonBitTracker.cpp [Alignment][NFC] Transition to MachineFrameInfo::getObjectAlign() 2020-04-01 14:08:28 +00:00
HexagonBitTracker.h
HexagonBlockRanges.cpp
HexagonBlockRanges.h
HexagonBranchRelaxation.cpp [Alignment][NFC] Deprecate Align::None() 2020-01-24 12:53:58 +01:00
HexagonCallingConv.td
HexagonCFGOptimizer.cpp
HexagonCommonGEP.cpp Remove SequentialType from the type heirarchy. 2020-04-06 17:03:49 -07:00
HexagonConstExtenders.cpp
HexagonConstPropagation.cpp [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonCopyToCombine.cpp [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonDepArch.h [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonDepArch.td [TableGen] Support combining AssemblerPredicates with ORs 2020-03-13 17:13:51 +00:00
HexagonDepDecoders.inc [Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm 2020-01-23 09:38:54 -06:00
HexagonDepIICHVX.td
HexagonDepIICScalar.td [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonDepInstrFormats.td
HexagonDepInstrInfo.td
HexagonDepITypes.h
HexagonDepITypes.td
HexagonDepMapAsm2Intrin.td [Hexagon] Map dcfetch intrinsic to Y2_dcfetchbo, not Y2_dcfetch 2020-02-28 14:19:20 -06:00
HexagonDepMappings.td
HexagonDepMask.h
HexagonDepOperands.td [Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm 2020-01-23 09:38:54 -06:00
HexagonDepTimingClasses.h
HexagonEarlyIfConv.cpp
HexagonExpandCondsets.cpp
HexagonFixupHwLoops.cpp [Alignment][NFC] Deprecate Align::None() 2020-01-24 12:53:58 +01:00
HexagonFrameLowering.cpp CodeGen: Use Register in TargetFrameLowering 2020-04-07 17:07:44 -04:00
HexagonFrameLowering.h CodeGen: Use Register in TargetFrameLowering 2020-04-07 17:07:44 -04:00
HexagonGenExtract.cpp
HexagonGenInsert.cpp
HexagonGenMux.cpp
HexagonGenPredicate.cpp
HexagonHardwareLoops.cpp CodeGen: Convert some TII hooks to use Register 2020-04-03 14:52:54 -04:00
HexagonHazardRecognizer.cpp
HexagonHazardRecognizer.h
HexagonIICHVX.td
HexagonIICScalar.td
HexagonInstrFormats.td
HexagonInstrFormatsV60.td
HexagonInstrFormatsV65.td
HexagonInstrInfo.cpp CodeGen: Convert some TII hooks to use Register 2020-04-03 14:52:54 -04:00
HexagonInstrInfo.h CodeGen: Convert some TII hooks to use Register 2020-04-03 14:52:54 -04:00
HexagonIntrinsics.td [Hexagon] Map dcfetch intrinsic to Y2_dcfetchbo, not Y2_dcfetch 2020-02-28 14:19:20 -06:00
HexagonIntrinsicsV5.td
HexagonIntrinsicsV60.td [Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1 2020-02-19 14:14:56 -06:00
HexagonISelDAGToDAG.cpp [Alignment][NFC] Deprecate getMaxAlignment 2020-03-18 14:48:45 +01:00
HexagonISelDAGToDAG.h [AsmPrinter] De-capitalize Emit{Function,BasicBlock]* and Emit{Start,End}OfAsmFile 2020-02-13 13:22:49 -08:00
HexagonISelDAGToDAGHVX.cpp [Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1 2020-02-19 14:14:56 -06:00
HexagonISelLowering.cpp [CallSite removal][TargetLowering] Replace ImmutableCallSite with CallBase 2020-04-13 13:50:15 -07:00
HexagonISelLowering.h CodeGen: Use Register in TargetLowering 2020-04-08 12:10:58 -04:00
HexagonISelLoweringHVX.cpp [Hexagon] Only allow single HVX vector loads/stores in lowering 2020-03-14 14:26:01 -05:00
HexagonLoopIdiomRecognition.cpp
HexagonMachineFunctionInfo.cpp
HexagonMachineFunctionInfo.h
HexagonMachineScheduler.cpp
HexagonMachineScheduler.h
HexagonMapAsm2IntrinV62.gen.td
HexagonMapAsm2IntrinV65.gen.td
HexagonMCInstLower.cpp [Hexagon][NFC] Rename VK_Hexagon_PCREL to VK_PCREL 2020-02-19 09:52:58 -06:00
HexagonNewValueJump.cpp
HexagonOperands.td
HexagonOptAddrMode.cpp Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
HexagonOptimizeSZextends.cpp
HexagonPatterns.td [Hexagon] Fix fshl/fshr -> combine() bug identified in D75114 2020-03-06 17:23:10 +00:00
HexagonPatternsHVX.td
HexagonPatternsV65.td
HexagonPeephole.cpp
HexagonPseudo.td
HexagonRDFOpt.cpp Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
HexagonRegisterInfo.cpp CodeGen: Use Register in TargetFrameLowering 2020-04-07 17:07:44 -04:00
HexagonRegisterInfo.h
HexagonRegisterInfo.td [Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1 2020-02-19 14:14:56 -06:00
HexagonSchedule.td [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonScheduleV5.td
HexagonScheduleV55.td
HexagonScheduleV60.td
HexagonScheduleV62.td
HexagonScheduleV65.td
HexagonScheduleV66.td
HexagonScheduleV67.td
HexagonScheduleV67T.td [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonSelectionDAGInfo.cpp
HexagonSelectionDAGInfo.h
HexagonSplitConst32AndConst64.cpp
HexagonSplitDouble.cpp CodeGen: Convert some TII hooks to use Register 2020-04-03 14:52:54 -04:00
HexagonStoreWidening.cpp [Alignment][NFC] Use Align version of getMachineMemOperand 2020-03-30 15:46:27 +00:00
HexagonSubtarget.cpp Provide operand indices to adjustSchedDependency 2020-04-17 11:08:44 +01:00
HexagonSubtarget.h Provide operand indices to adjustSchedDependency 2020-04-17 11:08:44 +01:00
HexagonTargetMachine.cpp
HexagonTargetMachine.h
HexagonTargetObjectFile.cpp [X86] Reland D71360 Clean up UseInitArray initialization for X86ELFTargetObjectFile 2020-03-20 21:57:34 -07:00
HexagonTargetObjectFile.h
HexagonTargetStreamer.h [MC] De-capitalize another set of MCStreamer::Emit* functions 2020-02-14 19:26:52 -08:00
HexagonTargetTransformInfo.cpp [SVE] Remove calls to getBitWidth from Hexagon 2020-04-14 11:09:49 -07:00
HexagonTargetTransformInfo.h [TTI][ARM][MVE] Refine gather/scatter cost model 2020-03-11 10:23:41 +00:00
HexagonVectorLoopCarriedReuse.cpp
HexagonVectorPrint.cpp [Hexagon] v67+ HVX register pairs should support either direction 2020-02-14 12:43:43 -06:00
HexagonVExtract.cpp
HexagonVLIWPacketizer.cpp [MC] Widen the functional unit type from 32 to 64 bits. 2020-02-24 09:37:00 +01:00
HexagonVLIWPacketizer.h [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
LLVMBuild.txt
RDFCopy.cpp Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
RDFCopy.h Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
RDFDeadCode.cpp Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
RDFDeadCode.h Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00