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Summary: Before this patch, `relaxInstruction` takes three arguments, the first argument refers to the instruction before relaxation and the third argument is the output instruction after relaxation. There are two quite strange things: 1) The first argument's type is `const MCInst &`, the third argument's type is `MCInst &`, but they may be aliased to the same variable 2) The backends of ARM, AMDGPU, RISC-V, Hexagon assume that the third argument is a fresh uninitialized `MCInst` even if `relaxInstruction` may be called like `relaxInstruction(Relaxed, STI, Relaxed)` in a loop. In this patch, we drop the thrid argument, and let `relaxInstruction` directly modify the given instruction. Also, this patch fixes the bug https://bugs.llvm.org/show_bug.cgi?id=45580, which is introduced by D77851, and breaks the assumption of ARM, AMDGPU, RISC-V, Hexagon. Reviewers: Razer6, MaskRay, jyknight, asb, luismarques, enderby, rtaylor, colinl, bcain Reviewed By: Razer6, MaskRay, bcain Subscribers: bcain, nickdesaulniers, nathanchance, wuzish, annita.zhang, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, tpr, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78364 |
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.. | ||
AsmParser | ||
Disassembler | ||
MCTargetDesc | ||
TargetInfo | ||
BitTracker.cpp | ||
BitTracker.h | ||
CMakeLists.txt | ||
Hexagon.h | ||
Hexagon.td | ||
HexagonArch.h | ||
HexagonAsmPrinter.cpp | ||
HexagonAsmPrinter.h | ||
HexagonBitSimplify.cpp | ||
HexagonBitTracker.cpp | ||
HexagonBitTracker.h | ||
HexagonBlockRanges.cpp | ||
HexagonBlockRanges.h | ||
HexagonBranchRelaxation.cpp | ||
HexagonCallingConv.td | ||
HexagonCFGOptimizer.cpp | ||
HexagonCommonGEP.cpp | ||
HexagonConstExtenders.cpp | ||
HexagonConstPropagation.cpp | ||
HexagonCopyToCombine.cpp | ||
HexagonDepArch.h | ||
HexagonDepArch.td | ||
HexagonDepDecoders.inc | ||
HexagonDepIICHVX.td | ||
HexagonDepIICScalar.td | ||
HexagonDepInstrFormats.td | ||
HexagonDepInstrInfo.td | ||
HexagonDepITypes.h | ||
HexagonDepITypes.td | ||
HexagonDepMapAsm2Intrin.td | ||
HexagonDepMappings.td | ||
HexagonDepMask.h | ||
HexagonDepOperands.td | ||
HexagonDepTimingClasses.h | ||
HexagonEarlyIfConv.cpp | ||
HexagonExpandCondsets.cpp | ||
HexagonFixupHwLoops.cpp | ||
HexagonFrameLowering.cpp | ||
HexagonFrameLowering.h | ||
HexagonGenExtract.cpp | ||
HexagonGenInsert.cpp | ||
HexagonGenMux.cpp | ||
HexagonGenPredicate.cpp | ||
HexagonHardwareLoops.cpp | ||
HexagonHazardRecognizer.cpp | ||
HexagonHazardRecognizer.h | ||
HexagonIICHVX.td | ||
HexagonIICScalar.td | ||
HexagonInstrFormats.td | ||
HexagonInstrFormatsV60.td | ||
HexagonInstrFormatsV65.td | ||
HexagonInstrInfo.cpp | ||
HexagonInstrInfo.h | ||
HexagonIntrinsics.td | ||
HexagonIntrinsicsV5.td | ||
HexagonIntrinsicsV60.td | ||
HexagonISelDAGToDAG.cpp | ||
HexagonISelDAGToDAG.h | ||
HexagonISelDAGToDAGHVX.cpp | ||
HexagonISelLowering.cpp | ||
HexagonISelLowering.h | ||
HexagonISelLoweringHVX.cpp | ||
HexagonLoopIdiomRecognition.cpp | ||
HexagonMachineFunctionInfo.cpp | ||
HexagonMachineFunctionInfo.h | ||
HexagonMachineScheduler.cpp | ||
HexagonMachineScheduler.h | ||
HexagonMapAsm2IntrinV62.gen.td | ||
HexagonMapAsm2IntrinV65.gen.td | ||
HexagonMCInstLower.cpp | ||
HexagonNewValueJump.cpp | ||
HexagonOperands.td | ||
HexagonOptAddrMode.cpp | ||
HexagonOptimizeSZextends.cpp | ||
HexagonPatterns.td | ||
HexagonPatternsHVX.td | ||
HexagonPatternsV65.td | ||
HexagonPeephole.cpp | ||
HexagonPseudo.td | ||
HexagonRDFOpt.cpp | ||
HexagonRegisterInfo.cpp | ||
HexagonRegisterInfo.h | ||
HexagonRegisterInfo.td | ||
HexagonSchedule.td | ||
HexagonScheduleV5.td | ||
HexagonScheduleV55.td | ||
HexagonScheduleV60.td | ||
HexagonScheduleV62.td | ||
HexagonScheduleV65.td | ||
HexagonScheduleV66.td | ||
HexagonScheduleV67.td | ||
HexagonScheduleV67T.td | ||
HexagonSelectionDAGInfo.cpp | ||
HexagonSelectionDAGInfo.h | ||
HexagonSplitConst32AndConst64.cpp | ||
HexagonSplitDouble.cpp | ||
HexagonStoreWidening.cpp | ||
HexagonSubtarget.cpp | ||
HexagonSubtarget.h | ||
HexagonTargetMachine.cpp | ||
HexagonTargetMachine.h | ||
HexagonTargetObjectFile.cpp | ||
HexagonTargetObjectFile.h | ||
HexagonTargetStreamer.h | ||
HexagonTargetTransformInfo.cpp | ||
HexagonTargetTransformInfo.h | ||
HexagonVectorLoopCarriedReuse.cpp | ||
HexagonVectorPrint.cpp | ||
HexagonVExtract.cpp | ||
HexagonVLIWPacketizer.cpp | ||
HexagonVLIWPacketizer.h | ||
LLVMBuild.txt | ||
RDFCopy.cpp | ||
RDFCopy.h | ||
RDFDeadCode.cpp | ||
RDFDeadCode.h |