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This update was done with the following bash script:
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while read NAME; do
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if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
TEMP=`mktemp -t temp`
cp $NAME $TEMP
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done
llvm-svn: 186280
252 lines
6.2 KiB
LLVM
252 lines
6.2 KiB
LLVM
; Test 32-bit signed division and remainder.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i32 @foo()
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; Test register division. The result is in the second of the two registers.
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define void @f1(i32 *%dest, i32 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: lgfr %r1, %r3
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; CHECK: dsgfr %r0, %r4
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; CHECK: st %r1, 0(%r2)
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; CHECK: br %r14
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%div = sdiv i32 %a, %b
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store i32 %div, i32 *%dest
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ret void
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}
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; Test register remainder. The result is in the first of the two registers.
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define void @f2(i32 *%dest, i32 %a, i32 %b) {
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; CHECK-LABEL: f2:
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; CHECK: lgfr %r1, %r3
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; CHECK: dsgfr %r0, %r4
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; CHECK: st %r0, 0(%r2)
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; CHECK: br %r14
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%rem = srem i32 %a, %b
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store i32 %rem, i32 *%dest
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ret void
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}
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; Test that division and remainder use a single instruction.
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define i32 @f3(i32 %dummy, i32 %a, i32 %b) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: %r2
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; CHECK: lgfr %r3, %r3
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; CHECK-NOT: %r2
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; CHECK: dsgfr %r2, %r4
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; CHECK-NOT: dsgfr
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; CHECK: or %r2, %r3
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; CHECK: br %r14
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%div = sdiv i32 %a, %b
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%rem = srem i32 %a, %b
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%or = or i32 %rem, %div
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ret i32 %or
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}
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; Check that the sign extension of the dividend is elided when the argument
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; is already sign-extended.
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define i32 @f4(i32 %dummy, i32 signext %a, i32 %b) {
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; CHECK-LABEL: f4:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsgfr %r2, %r4
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; CHECK-NOT: dsgfr
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; CHECK: or %r2, %r3
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; CHECK: br %r14
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%div = sdiv i32 %a, %b
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%rem = srem i32 %a, %b
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%or = or i32 %rem, %div
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ret i32 %or
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}
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; Test that memory dividends are loaded using sign extension (LGF).
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define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK-LABEL: f5:
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; CHECK-NOT: %r2
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; CHECK: lgf %r3, 0(%r3)
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; CHECK-NOT: %r2
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; CHECK: dsgfr %r2, %r4
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; CHECK-NOT: dsgfr
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; CHECK: or %r2, %r3
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; CHECK: br %r14
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%a = load i32 *%src
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%div = sdiv i32 %a, %b
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%rem = srem i32 %a, %b
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%or = or i32 %rem, %div
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ret i32 %or
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}
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; Test memory division with no displacement.
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define void @f6(i32 *%dest, i32 %a, i32 *%src) {
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; CHECK-LABEL: f6:
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; CHECK: lgfr %r1, %r3
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; CHECK: dsgf %r0, 0(%r4)
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; CHECK: st %r1, 0(%r2)
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; CHECK: br %r14
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%b = load i32 *%src
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%div = sdiv i32 %a, %b
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store i32 %div, i32 *%dest
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ret void
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}
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; Test memory remainder with no displacement.
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define void @f7(i32 *%dest, i32 %a, i32 *%src) {
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; CHECK-LABEL: f7:
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; CHECK: lgfr %r1, %r3
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; CHECK: dsgf %r0, 0(%r4)
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; CHECK: st %r0, 0(%r2)
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; CHECK: br %r14
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%b = load i32 *%src
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%rem = srem i32 %a, %b
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store i32 %rem, i32 *%dest
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ret void
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}
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; Test both memory division and memory remainder.
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define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK-LABEL: f8:
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; CHECK-NOT: %r2
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; CHECK: lgfr %r3, %r3
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; CHECK-NOT: %r2
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; CHECK: dsgf %r2, 0(%r4)
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; CHECK-NOT: {{dsgf|dsgfr}}
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; CHECK: or %r2, %r3
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; CHECK: br %r14
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%b = load i32 *%src
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%div = sdiv i32 %a, %b
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%rem = srem i32 %a, %b
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%or = or i32 %rem, %div
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ret i32 %or
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}
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; Check the high end of the DSGF range.
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define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK-LABEL: f9:
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; CHECK: dsgf %r2, 524284(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131071
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%b = load i32 *%ptr
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%rem = srem i32 %a, %b
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ret i32 %rem
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK-LABEL: f10:
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; CHECK: agfi %r4, 524288
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; CHECK: dsgf %r2, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131072
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%b = load i32 *%ptr
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%rem = srem i32 %a, %b
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ret i32 %rem
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}
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; Check the high end of the negative aligned DSGF range.
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define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK-LABEL: f11:
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; CHECK: dsgf %r2, -4(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -1
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%b = load i32 *%ptr
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%rem = srem i32 %a, %b
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ret i32 %rem
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}
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; Check the low end of the DSGF range.
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define i32 @f12(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK-LABEL: f12:
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; CHECK: dsgf %r2, -524288(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131072
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%b = load i32 *%ptr
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%rem = srem i32 %a, %b
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ret i32 %rem
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f13(i32 %dummy, i32 %a, i32 *%src) {
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; CHECK-LABEL: f13:
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; CHECK: agfi %r4, -524292
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; CHECK: dsgf %r2, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131073
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%b = load i32 *%ptr
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%rem = srem i32 %a, %b
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ret i32 %rem
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}
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; Check that DSGF allows an index.
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define i32 @f14(i32 %dummy, i32 %a, i64 %src, i64 %index) {
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; CHECK-LABEL: f14:
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; CHECK: dsgf %r2, 524287(%r5,%r4)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i32 *
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%b = load i32 *%ptr
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%rem = srem i32 %a, %b
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ret i32 %rem
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}
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; Make sure that we still use DSGFR rather than DSGR in cases where
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; a load and division cannot be combined.
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define void @f15(i32 *%dest, i32 *%src) {
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; CHECK-LABEL: f15:
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; CHECK: l [[B:%r[0-9]+]], 0(%r3)
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; CHECK: brasl %r14, foo@PLT
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; CHECK: lgfr %r1, %r2
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; CHECK: dsgfr %r0, [[B]]
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; CHECK: br %r14
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%b = load i32 *%src
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%a = call i32 @foo()
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%div = sdiv i32 %a, %b
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store i32 %div, i32 *%dest
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ret void
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}
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; Check that divisions of spilled values can use DSGF rather than DSGFR.
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define i32 @f16(i32 *%ptr0) {
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; CHECK-LABEL: f16:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: dsgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr i32 *%ptr0, i64 2
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%ptr2 = getelementptr i32 *%ptr0, i64 4
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%ptr3 = getelementptr i32 *%ptr0, i64 6
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%ptr4 = getelementptr i32 *%ptr0, i64 8
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%ptr5 = getelementptr i32 *%ptr0, i64 10
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%ptr6 = getelementptr i32 *%ptr0, i64 12
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%ptr7 = getelementptr i32 *%ptr0, i64 14
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%ptr8 = getelementptr i32 *%ptr0, i64 16
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%ptr9 = getelementptr i32 *%ptr0, i64 18
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%val0 = load i32 *%ptr0
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%val1 = load i32 *%ptr1
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%val2 = load i32 *%ptr2
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%val3 = load i32 *%ptr3
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%val4 = load i32 *%ptr4
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%val5 = load i32 *%ptr5
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%val6 = load i32 *%ptr6
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%val7 = load i32 *%ptr7
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%val8 = load i32 *%ptr8
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%val9 = load i32 *%ptr9
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%ret = call i32 @foo()
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%div0 = sdiv i32 %ret, %val0
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%div1 = sdiv i32 %div0, %val1
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%div2 = sdiv i32 %div1, %val2
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%div3 = sdiv i32 %div2, %val3
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%div4 = sdiv i32 %div3, %val4
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%div5 = sdiv i32 %div4, %val5
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%div6 = sdiv i32 %div5, %val6
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%div7 = sdiv i32 %div6, %val7
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%div8 = sdiv i32 %div7, %val8
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%div9 = sdiv i32 %div8, %val9
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ret i32 %div9
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}
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