mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 03:02:36 +01:00
c1329a6c94
Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267
68 lines
2.2 KiB
YAML
68 lines
2.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
|
|
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
|
|
|
|
---
|
|
name: cvt_pk_i16_vsv
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0, $vgpr0
|
|
; GCN-LABEL: name: cvt_pk_i16_vsv
|
|
; GCN: liveins: $sgpr0, $vgpr0
|
|
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GCN: [[V_CVT_PK_I16_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_I16_I32_e64 [[COPY]], [[COPY1]], implicit $exec
|
|
; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_I16_I32_e64_]]
|
|
%0:sgpr(s32) = COPY $sgpr0
|
|
%1:vgpr(s32) = COPY $vgpr0
|
|
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.i16), %0, %1
|
|
S_ENDPGM 0, implicit %2
|
|
...
|
|
|
|
---
|
|
name: cvt_pk_i16_vvs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0, $vgpr0
|
|
|
|
; GCN-LABEL: name: cvt_pk_i16_vvs
|
|
; GCN: liveins: $sgpr0, $vgpr0
|
|
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
; GCN: [[V_CVT_PK_I16_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_I16_I32_e64 [[COPY]], [[COPY1]], implicit $exec
|
|
; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_I16_I32_e64_]]
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
%1:sgpr(s32) = COPY $sgpr0
|
|
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.i16), %0, %1
|
|
S_ENDPGM 0, implicit %2
|
|
...
|
|
|
|
---
|
|
name: cvt_pk_i16_vvv
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0, $vgpr1
|
|
; GCN-LABEL: name: cvt_pk_i16_vvv
|
|
; GCN: liveins: $vgpr0, $vgpr1
|
|
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
|
; GCN: [[V_CVT_PK_I16_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_I16_I32_e64 [[COPY]], [[COPY1]], implicit $exec
|
|
; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_I16_I32_e64_]]
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
%1:vgpr(s32) = COPY $vgpr1
|
|
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.i16), %0, %1
|
|
S_ENDPGM 0, implicit %2
|
|
...
|