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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 10:42:39 +01:00
llvm-mirror/test/CodeGen/AMDGPU
Nicolai Hähnle 5d6415281f [IR] Memory intrinsics are not unconditionally nosync
Remove the `nosync` attribute from the memory intrinsic definitions
(i.e. memset, memcpy, memmove).

Like native memory accesses, memory intrinsics can be volatile. This is
indicated by an immarg in the intrinsic call. All else equal, a volatile
memory intrinsic is `sync`, so we cannot annotate the intrinsic functions
themselves as `nosync`. The attributor and function-attr passes know to
take the volatile bit into account.

Since `nosync` is a default attribute, this means we have to stop using
the DefaultAttrIntrinsic tablegen class for memory intrinsics, and
specify all default attributes other than `nosync` explicitly.

Most of the test changes are trivial churn, but one test case
(in nosync.ll) was in fact incorrect before this change.

Differential Revision: https://reviews.llvm.org/D102295
2021-05-21 03:40:59 +02:00
..
GlobalISel Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" 2021-05-19 09:29:19 -07:00
32-bit-local-address-space.ll
aa-points-to-constant-memory.ll
acc-ldst.ll
accvgpr-copy.mir [AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks 2021-04-30 14:10:50 +01:00
add3.ll
add_i1.ll
add_i64.ll
add_i128.ll
add_shl.ll
add-debug.ll
add.i16.ll
add.ll
add.v2i16.ll
addrspacecast-captured.ll
addrspacecast-constantexpr.ll [IR] Memory intrinsics are not unconditionally nosync 2021-05-21 03:40:59 +02:00
addrspacecast-initializer-unsupported.ll
addrspacecast-initializer.ll
addrspacecast.ll
adjust-writemask-invalid-copy.ll
adjust-writemask-vectorized.ll
agpr-csr.ll AMDGPU: Add missing runline to test 2021-04-29 20:59:22 -04:00
agpr-register-count.ll
agpr-remat.ll
alignbit-pat.ll
alloc-aligned-tuples-gfx90a.mir
alloc-aligned-tuples-gfx908.mir
alloc-all-regs-reserved-in-class.mir
alloca.ll
always-uniform.ll
amd.endpgm.ll
amdgcn-ieee.ll
amdgcn-load-offset-from-reg.ll
amdgcn.bitcast.ll
amdgcn.private-memory.ll
amdgpu-alias-analysis.ll
amdgpu-codegenprepare-fdiv.ll
amdgpu-codegenprepare-fold-binop-select.ll Reapply [ConstantFold] Fold more operations to poison 2021-05-13 16:04:12 +02:00
amdgpu-codegenprepare-i16-to-i32.ll
amdgpu-codegenprepare-idiv.ll [AMDGPU] Update SCC defs to VCC when uses are changed to VCC 2021-05-14 18:05:05 -04:00
amdgpu-codegenprepare-mul24.ll
amdgpu-function-calls-option.ll
amdgpu-inline.ll
amdgpu-late-codegenprepare.ll AMDGPU: Fix assert on constant load from addrspacecasted pointer 2021-05-11 20:12:20 -04:00
amdgpu-mul24-knownbits.ll
amdgpu-reloc-const.ll
amdgpu-shader-calling-convention.ll
amdgpu-unroll-threshold.ll
amdgpu.private-memory.ll
amdgpu.work-item-intrinsics.deprecated.ll
amdhsa-trap-num-sgprs.ll
amdpal_scratch_mergedshader.ll
amdpal-callable.ll [AMDGPU] getMemOperandsWithOffset: add vaddr operand for stack access BUF instructions 2021-05-14 10:10:43 +01:00
amdpal-cs.ll
amdpal-elf.ll
amdpal-es.ll
amdpal-gs.ll
amdpal-hs.ll
amdpal-ls.ll
amdpal-msgpack-cs.ll
amdpal-msgpack-default.ll
amdpal-msgpack-denormal.ll
amdpal-msgpack-dx10-clamp.ll
amdpal-msgpack-es.ll
amdpal-msgpack-gs.ll
amdpal-msgpack-hs.ll
amdpal-msgpack-ieee.ll
amdpal-msgpack-ls.ll
amdpal-msgpack-ps.ll
amdpal-msgpack-psenable.ll
amdpal-msgpack-vs.ll
amdpal-ps.ll
amdpal-psenable.ll
amdpal-vs.ll
amdpal.ll
and_or.ll
and-gcn.ll
and.ll
andorbitset.ll
andorn2.ll
andorxorinvimm.ll
annotate-kernel-features-hsa-call.ll
annotate-kernel-features-hsa.ll
annotate-kernel-features.ll
annotate-noclobber.ll
anonymous-gv.ll
any_extend_vector_inreg.ll
anyext.ll
are-loads-from-same-base-ptr.ll
array-ptr-calc-i32.ll
array-ptr-calc-i64.ll
ashr.v2i16.ll
asm-printer-check-vcc.mir
at-least-one-def-value-assert.mir
atomic_cmp_swap_local.ll
atomic_load_add.ll
atomic_load_local.ll
atomic_load_sub.ll
atomic_optimizations_buffer.ll
atomic_optimizations_global_pointer.ll
atomic_optimizations_local_pointer.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
atomic_optimizations_pixelshader.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
atomic_optimizations_raw_buffer.ll
atomic_optimizations_struct_buffer.ll
atomic_store_local.ll
atomicrmw-nand.ll [AMDGPU] Revise handling of preexisting waitcnt 2021-05-05 17:21:33 -07:00
attr-amdgpu-flat-work-group-size-v3.ll
attr-amdgpu-flat-work-group-size-vgpr-limit.ll
attr-amdgpu-flat-work-group-size.ll
attr-amdgpu-num-sgpr.ll
attr-amdgpu-num-vgpr.ll
attr-amdgpu-waves-per-eu.ll
attr-unparseable.ll
barrier-elimination.ll
basic-branch.ll
basic-call-return.ll
basic-loop.ll
bfe_uint.ll
bfe-combine.ll
bfe-patterns.ll
bfi_int.ll
bfm.ll
big_alu.ll
bitcast-constant-to-vector.ll
bitcast-v4f16-v4i16.ll
bitcast-vector-extract.ll
bitreverse-inline-immediates.ll
bitreverse.ll
br_cc.f16.ll
branch-condition-and.ll
branch-relax-bundle.ll
branch-relax-spill.ll
branch-relaxation-debug-info.mir
branch-relaxation-gfx10-branch-offset-bug.ll
branch-relaxation-inst-size-gfx10.ll
branch-relaxation.ll
branch-uniformity.ll
break-smem-soft-clauses.mir
break-vmem-soft-clauses.mir
bswap.ll
buffer-intrinsics-mmo-offsets.ll
buffer-schedule.ll
bug-sdag-scheduler-cycle.ll
bug-vopc-commute.ll
build_vector.ll
build-vector-insert-elt-infloop.ll
build-vector-packed-partial-undef.ll
bundle-latency.mir
bypass-div.ll
byval-frame-setup.ll
call_fs.ll
call-argument-types.ll [TargetLowering] Only inspect attributes in the arguments for ArgListEntry 2021-05-18 14:30:22 -07:00
call-constant.ll AMDGPU/GlobalISel: Implement tail calls 2021-05-13 18:57:42 -04:00
call-constexpr.ll
call-encoding.ll
call-graph-register-usage.ll
call-preserved-registers.ll
call-return-types.ll
call-skip.ll
call-to-kernel-undefined.ll
call-to-kernel.ll
call-waitcnt.ll
call-waw-waitcnt.mir
callee-frame-setup.ll
callee-special-input-sgprs-fixed-abi.ll
callee-special-input-sgprs.ll
callee-special-input-vgprs-packed.ll [TargetLowering] Only inspect attributes in the arguments for ArgListEntry 2021-05-18 14:30:22 -07:00
callee-special-input-vgprs.ll [TargetLowering] Only inspect attributes in the arguments for ArgListEntry 2021-05-18 14:30:22 -07:00
calling-conventions.ll
captured-frame-index.ll
carryout-selection.ll
cayman-loop-bug.ll
cc-sgpr-limit.ll
cc-sgpr-over-limit.ll
cc-update.ll
cf_end.ll
cf-loop-on-constant.ll
cf-stack-bug.ll
cgp-addressing-modes-flat.ll
cgp-addressing-modes-gfx908.ll
cgp-addressing-modes-gfx1030.ll
cgp-addressing-modes.ll
cgp-bitfield-extract.ll
chain-hi-to-lo.ll
change-scc-to-vcc.mir [AMDGPU] Update SCC defs to VCC when uses are changed to VCC 2021-05-14 18:05:05 -04:00
clamp-modifier.ll
clamp-omod-special-case.mir
clamp.ll
cluster_stores.ll [AMDGPU] Do not clause NSA instructions 2021-05-14 12:54:56 +09:00
cluster-flat-loads-postra.mir
cluster-flat-loads.mir
cmp_shrink.mir
cndmask-no-def-vcc.ll
coalesce-identity-copies-undef-subregs.mir
coalesce-vgpr-alignment.ll
coalescer_distribute.ll
coalescer_remat.ll [AMDGPU] Switch AnnotateUniformValues to MemorySSA 2021-05-05 18:34:41 -07:00
coalescer-extend-pruned-subrange.mir
coalescer-identical-values-undef.mir
coalescer-removepartial-extend-undef-subrange.mir
coalescer-subranges-another-copymi-not-live.mir
coalescer-subranges-another-prune-error.mir
coalescer-subranges-prune-kill-copy.mir
coalescer-subreg-join.mir
coalescer-subregjoin-fullcopy.mir
coalescer-with-subregs-bad-identical.mir
coalescing_makes_lanes_undef.mir
coalescing-subreg-was-undef-but-became-def.mir
coalescing-with-subregs-in-loop-bug.mir
code-object-v3.ll
codegen-prepare-addrmode-sext.ll
collapse-endcf2.mir
collapse-endcf-broken.mir
collapse-endcf.ll
collapse-endcf.mir
combine_vloads.ll
combine-add-zext-xor.ll
combine-and-sext-bool.ll
combine-cond-add-sub.ll
combine-ftrunc.ll
comdat.ll
commute_modifiers.ll
commute-compares.ll
commute-shifts.ll
commute-vop3.mir [AMDGPU] Make some VOP3 insts commutable 2021-04-28 13:59:08 -04:00
complex-folding.ll
computeKnownBits-scalar-to-vector-crash.ll
computeNumSignBits-mul.ll
concat_vectors.ll
constant-address-space-32bit.ll
constant-fold-imm-immreg.mir
constant-fold-mi-operands.ll
control-flow-fastregalloc.ll
control-flow-optnone.ll
convergent-inlineasm.ll
copy_phys_vgpr64.mir
copy-illegal-type.ll
copy-overlap-vgpr-kill.mir
copy-to-reg.ll
couldnt-join-subrange-3.mir
cross-block-use-is-not-abi-copy.ll
cse-phi-incoming-val.ll
csr-gfx10.ll
csr-sgpr-spill-live-ins.mir
ctlz_zero_undef.ll
ctlz.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
ctpop16.ll
ctpop64.ll
ctpop.ll
cttz_zero_undef.ll
cube.ll
cvt_f32_ubyte.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
cvt_flr_i32_f32.ll
cvt_rpi_i32_f32.ll
dag-divergence-atomic.ll
dag-divergence.ll
dagcomb-shuffle-vecextend-non2.ll
dagcombine-reassociate-bug.ll
dagcombine-select.ll
dagcombine-setcc-select.ll
dagcombiner-bug-illegal-vec4-int-to-fp.ll
dbg-value-ends-sched-region.mir
dce-disjoint-intervals.mir
dead_copy.mir
dead-lane.mir
dead-machine-elim-after-dead-lane.ll
debug_frame.ll [MCAsmInfo] Support UsesCFIForDebug for targets with no exception handling 2021-05-06 04:53:45 +05:30
debug-value2.ll
debug-value-scheduler-crash.mir
debug-value.ll
debug.ll
default-fp-mode.ll
detect-dead-lanes.mir
direct-indirect-call.ll
directive-amdgcn-target.ll [AMDGPU] Add gfx1034 target 2021-05-13 14:25:18 -04:00
disable_form_clauses.ll
disconnected-predset-break-bug.ll
div_i128.ll
diverge-extra-formal-args.ll
diverge-interp-mov-lower.ll
diverge-switch-default.ll
divergence-at-use.ll
divergent-branch-uniform-condition.ll
divrem24-assume.ll
dpp64_combine.ll
dpp64_combine.mir
dpp_combine.ll
dpp_combine.mir
drop-mem-operand-move-smrd.ll
ds_read2_offset_order.ll
ds_read2_superreg.ll
ds_read2.ll
ds_read2st64.ll
ds_write2.ll
ds_write2st64.ll
ds-alignment.ll
ds-combine-large-stride.ll
ds-combine-with-dependence.ll
ds-negative-offset-addressing-mode-loop.ll
ds-sub-offset.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
duplicate-attribute-indirect.ll
dynamic_stackalloc.ll
early-if-convert-cost.ll
early-if-convert.ll
early-inline-alias.ll
early-inline.ll
early-tailduplicator-nophis.mir
early-term.mir
elf-header-flags-mach.ll [AMDGPU] Add gfx1034 target 2021-05-13 14:25:18 -04:00
elf-header-flags-sramecc.ll
elf-header-flags-xnack.ll
elf-header-osabi.ll
elf-notes.ll
elf.ll
elf.metadata.ll
elf.r600.ll
else.ll
empty-function.ll
enable-no-signed-zeros-fp-math.ll
endcf-loop-header.ll
endpgm-dce.mir
enqueue-kernel.ll
exceed-max-sgprs.ll
expand-atomicrmw-syncscope.ll
expand-scalar-carry-out-select-user.ll
expand-si-indirect.mir
extend-bit-ops-i16.ll
extload-align.ll
extload-private.ll
extload.ll
extra-sroa-after-unroll.ll
extract_subvector_vec4_vec3.ll
extract_vector_dynelt.ll
extract_vector_elt-f16.ll
extract_vector_elt-f64.ll
extract_vector_elt-i8.ll
extract_vector_elt-i16.ll
extract_vector_elt-i64.ll
extract-load-i1.ll
extract-lowbits.ll
extract-subvector-equal-length.ll
extract-subvector.ll
extract-vector-elt-build-vector-combine.ll
extractelt-to-trunc.ll
fabs.f16.ll
fabs.f64.ll
fabs.ll
fadd64.ll
fadd-fma-fmul-combine.ll
fadd.f16.ll
fadd.ll
fail-select-buffer-atomic-fadd.ll
fast-ra-kills-vcc.mir
fast-regalloc-bundles.mir
fast-unaligned-load-store.global.ll [AMDGPU] Make some VOP3 insts commutable 2021-04-28 13:59:08 -04:00
fast-unaligned-load-store.private.ll [AMDGPU] Make some VOP3 insts commutable 2021-04-28 13:59:08 -04:00
fastregalloc-illegal-subreg-physreg.mir
fastregalloc-self-loop-heuristic.mir
fcanonicalize-elimination.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
fcanonicalize.f16.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
fcanonicalize.ll
fceil64.ll
fceil.ll
fcmp64.ll
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.f16.ll
fcmp.ll
fconst64.ll
fcopysign.f16.ll
fcopysign.f32.ll
fcopysign.f64.ll
fdiv32-to-rcp-folding.ll
fdiv-nofpexcept.ll
fdiv.f16.ll
fdiv.f64.ll
fdiv.ll
fdot2.ll
fence-barrier.ll
fence-lds-read2-write2.ll
fetch-limits.r600.ll
fetch-limits.r700+.ll
fexp.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
ffloor.f64.ll
ffloor.ll
fix-frame-ptr-reg-copy-livein.ll
fix-sgpr-copies.mir
fix-vgpr-copies.mir
fix-wwm-vgpr-copy.ll
flat_atomics_i64.ll
flat_atomics.ll
flat-address-space.ll
flat-error-unsupported-gpu-hsa.ll
flat-for-global-subtarget-feature.ll
flat-load-clustering.mir
flat-offset-bug.ll
flat-scratch-fold-fi.mir
flat-scratch-reg.ll
flat-scratch.ll [AMDGPU] Restrict immediate scratch offsets 2021-05-07 14:51:32 +02:00
floor.ll
fma-combine.ll
fma.f64.ll
fma.ll
fmac.sdwa.ll
fmad-formation-fmul-distribute-denormal-mode.ll
fmad.ll
fmax3.f64.ll
fmax3.ll
fmax_legacy.f16.ll
fmax_legacy.f64.ll
fmax_legacy.ll
fmax.ll
fmaxnum.f64.ll
fmaxnum.ll
fmaxnum.r600.ll
fmed3.ll
fmin3.ll
fmin_fmax_legacy.amdgcn.ll
fmin_legacy.f16.ll
fmin_legacy.f64.ll
fmin_legacy.ll
fmin.ll
fminnum.f64.ll
fminnum.ll
fminnum.r600.ll
fmul64.ll
fmul-2-combine-multi-use.ll
fmul.f16.ll
fmul.ll
fmuladd.f16.ll
fmuladd.f32.ll
fmuladd.f64.ll
fmuladd.v2f16.ll
fnearbyint.ll
fneg-combines.ll
fneg-combines.si.ll
fneg-fabs.f16.ll
fneg-fabs.f64.ll
fneg-fabs.ll
fneg-fold-legalize-dag-increase-insts.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
fneg.f16.ll
fneg.f64.ll
fneg.ll
fold_16bit_imm.mir
fold_acc_copy_into_valu.mir
fold-cndmask-wave32.mir
fold-cndmask.mir
fold-fi-mubuf.mir
fold-fi-operand-shrink.mir
fold-fmul-to-neg-abs.ll
fold-imm-copy.mir
fold-imm-f16-f32.mir
fold-immediate-operand-shrink-with-carry.mir
fold-immediate-operand-shrink.mir
fold-immediate-output-mods.mir
fold-implicit-operand.mir
fold-multiple.mir
fold-operands-order.mir
fold-operands-remove-m0-redef.mir
fold-over-exec.mir
fold-readlane.mir
fold-reload-into-exec.mir
fold-reload-into-m0.mir
fold-sgpr-copy.mir
fold-sgpr-multi-imm.mir
fold-vgpr-copy.mir
force-alwaysinline-lds-global-address-codegen.ll
force-alwaysinline-lds-global-address.ll
fp16_to_fp32.ll
fp16_to_fp64.ll
fp32_to_fp16.ll
fp64-atomics-gfx90a.ll [AMDGPU] Do not check denorm for LDS FP atomic with unsafe flag 2021-05-17 16:53:09 -07:00
fp_to_sint.f64.ll
fp_to_sint.ll [DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts 2021-05-07 13:12:30 +01:00
fp_to_uint.f64.ll
fp_to_uint.ll [DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts 2021-05-07 13:12:30 +01:00
fp-atomic-to-s_denormmode.mir
fp-classify.ll
fpext-free.ll
fpext.f16.ll
fpext.ll
fpow.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
fptosi.f16.ll [AMDGPU] Select V_CVT_*16_F16 more often 2021-05-05 08:57:51 +01:00
fptoui.f16.ll [AMDGPU] Select V_CVT_*16_F16 more often 2021-05-05 08:57:51 +01:00
fptrunc.f16.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
fptrunc.ll
fract.f64.ll
fract.ll
frame-index-elimination.ll
frame-lowering-entry-all-sgpr-used.mir
frame-lowering-fp-adjusted.mir
frame-setup-without-sgpr-to-vgpr-spills.ll
frem.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
fshl.ll
fshr.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
fsqrt.f64.ll
fsqrt.ll
fsub64.ll
fsub.f16.ll
fsub.ll
ftrunc.f64.ll
ftrunc.ll
function-args.ll
function-call-relocs.ll
function-returns.ll
gds-atomic.ll
gep-address-space.ll
gfx10-vop-literal.ll
gfx90a-enc.ll
gfx902-without-xnack.ll
gfx-callable-argument-types.ll [TargetLowering] Only inspect attributes in the arguments for ArgListEntry 2021-05-18 14:30:22 -07:00
gfx-callable-preserved-registers.ll
gfx-callable-return-types.ll
global_atomics_i64.ll [AMDGPU] Improve global SADDR selection 2021-05-05 14:44:21 -07:00
global_atomics.ll [AMDGPU] Improve global SADDR selection 2021-05-05 14:44:21 -07:00
global_smrd_cfg.ll
global_smrd.ll
global-atomics-fp-wrong-subtarget.ll
global-atomics-fp.ll [AMDGPU] Only allow global fp atomics with unsafe option 2021-05-13 08:52:20 -07:00
global-constant.ll
global-directive.ll
global-extload-i16.ll
global-load-saddr-to-vaddr.ll AMDGPU: Fix assert when rewriting saddr d16 loads 2021-05-14 13:24:19 -04:00
global-saddr-atomics.gfx908.ll
global-saddr-atomics.gfx1030.ll
global-saddr-atomics.ll
global-saddr-load.ll [AMDGPU] Improve global SADDR selection 2021-05-05 14:44:21 -07:00
global-saddr-store.ll
global-smrd-unknown.ll [AMDGPU] Switch AnnotateUniformValues to MemorySSA 2021-05-05 18:34:41 -07:00
global-variable-relocs.ll
greedy-broken-ssa-verifier-error.mir
gv-const-addrspace.ll
gv-offset-folding.ll
gws-hazards.mir
half.ll
hard-clauses.mir [AMDGPU] Do not clause NSA instructions 2021-05-14 12:54:56 +09:00
hazard-buffer-store-v-interp.mir
hazard-hidden-bundle.mir
hazard-in-bundle.mir
hazard-inlineasm.mir
hazard-kill.mir
hazard-pass-ordering.mir
hazard-recognizer-meta-insts.mir
hazard.mir
hip.extern.shared.array.ll
hoist-cond.ll
hsa-default-device.ll
hsa-fp-mode.ll
hsa-func-align.ll
hsa-func.ll
hsa-globals.ll
hsa-group-segment.ll
hsa-metadata-deduce-ro-arg-v3.ll
hsa-metadata-deduce-ro-arg.ll
hsa-metadata-enqueue-kernel-v3.ll
hsa-metadata-enqueue-kernel.ll
hsa-metadata-from-llvm-ir-full-v3.ll
hsa-metadata-from-llvm-ir-full.ll
hsa-metadata-hidden-args-v3.ll
hsa-metadata-hidden-args.ll
hsa-metadata-hostcall-absent-v3.ll
hsa-metadata-hostcall-absent.ll
hsa-metadata-hostcall-present-v3.ll
hsa-metadata-hostcall-present.ll
hsa-metadata-images-v3.ll
hsa-metadata-images.ll
hsa-metadata-invalid-ocl-version-1-v3.ll
hsa-metadata-invalid-ocl-version-1.ll
hsa-metadata-invalid-ocl-version-2-v3.ll
hsa-metadata-invalid-ocl-version-2.ll
hsa-metadata-invalid-ocl-version-3-v3.ll
hsa-metadata-invalid-ocl-version-3.ll
hsa-metadata-kernel-code-props-v3.ll
hsa-metadata-kernel-code-props.ll
hsa-metadata-wavefrontsize.ll
hsa-note-no-func.ll
hsa.ll
huge-number-operand-folds.mir
huge-private-buffer.ll
i1_copy_phi_with_phi_incoming_value.mir
i1-copies-rpo.mir [AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks 2021-04-30 14:10:50 +01:00
i1-copy-from-loop.ll
i1-copy-implicit-def.ll
i1-copy-phi-uniform-branch.ll
i1-copy-phi.ll
i8-to-double-to-float.ll
icmp64.ll
icmp-select-sete-reverse-args.ll
icmp.i16.ll
idiv-licm.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
idot2.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
idot4s.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
idot4u.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
idot8s.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
idot8u.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
illegal-sgpr-to-vgpr-copy.ll
image_ls_mipmap_zero.ll
image-attributes.ll
image-load-d16-tfe.ll
image-resource-id.ll
image-sample-waterfall.ll
image-schedule.ll
img-nouse-adjust.ll
imm16.ll
imm.ll
immv216.ll
implicit-def-muse.ll
indirect-addressing-si-gfx9.ll
indirect-addressing-si-noopt.ll
indirect-addressing-si-pregfx9.ll
indirect-addressing-si.ll
indirect-addressing-term.ll
indirect-call.ll
indirect-private-64.ll
infer-addrpace-pipeline.ll
infer-uniform-load-shader.ll
infinite-loop-evergreen.ll
infinite-loop.ll
inline-asm.i128.ll
inline-asm.ll
inline-attr.ll
inline-calls.ll
inline-constraints.ll
inline-maxbb.ll
inlineasm-16.ll
inlineasm-illegal-type.ll
inlineasm-packed.ll
InlineAsmCrash.ll
input-mods.ll
insert_subreg.ll
insert_vector_dynelt.ll
insert_vector_elt.ll
insert_vector_elt.v2i16.ll
insert_vector_elt.v2i16.subtest-nosaddr.ll
insert_vector_elt.v2i16.subtest-saddr.ll
insert-branch-w32.mir
insert-skip-from-vcc.mir
insert-skips-flat-vmem-ds.mir
insert-skips-gws.mir
insert-skips-ignored-insts.mir
insert-subvector-unused-scratch.ll
insert-waitcnts-callee.mir
insert-waitcnts-exp.mir
inserted-wait-states.mir
internalize.ll
invalid-addrspacecast.ll
invalid-alloca.ll
invariant-load-no-alias-store.ll
invert-br-undef-vcc.mir
ipra-regmask.ll
ipra.ll
jump-address.ll
kcache-fold.ll
kernarg-size.ll
kernarg-stack-alignment.ll
kernel-args.ll
kernel-argument-dag-lowering.ll
kill-infinite-loop.ll
known-never-nan.ll
known-never-snan.ll
knownbits-recursion.ll
large-alloca-compute.ll
large-alloca-graphics.ll
large-constant-initializer.ll
large-work-group-promote-alloca.ll
lcssa-optnone.ll
lds_atomic_f32.ll
lds-alignment.ll
lds-bounds.ll
lds-branch-vmem-hazard.mir
lds-global-non-entry-func.ll
lds-initializer.ll
lds-m0-init-in-loop.ll
lds-misaligned-bug.ll
lds-oqap-crash.ll
lds-output-queue.ll
lds-relocs.ll
lds-size.ll
lds-zero-initializer.ll
legalize-fp-load-invariant.ll
legalizedag-bug-expand-setcc.ll
limit-coalesce.mir
limit-soft-clause-reg-pressure.mir
lit.local.cfg
literals.ll
liveness.mir
llc-pipeline.ll [AMDGPU] Disable the SIFormMemoryClauses pass at -O1 2021-05-12 11:51:59 -04:00
llvm.amdgcn.alignb.ll
llvm.amdgcn.atomic.csub.ll
llvm.amdgcn.atomic.dec.ll
llvm.amdgcn.atomic.fadd.gfx90a.ll
llvm.amdgcn.atomic.fadd.ll
llvm.amdgcn.atomic.inc.ll
llvm.amdgcn.ballot.i32.ll
llvm.amdgcn.ballot.i64.ll
llvm.amdgcn.buffer.atomic.ll
llvm.amdgcn.buffer.load.dwordx3.ll
llvm.amdgcn.buffer.load.format.d16.ll
llvm.amdgcn.buffer.load.format.ll
llvm.amdgcn.buffer.load.ll
llvm.amdgcn.buffer.store.dwordx3.ll
llvm.amdgcn.buffer.store.format.d16.ll
llvm.amdgcn.buffer.store.format.ll
llvm.amdgcn.buffer.store.ll
llvm.amdgcn.buffer.wbinvl1.ll
llvm.amdgcn.buffer.wbinvl1.sc.ll
llvm.amdgcn.buffer.wbinvl1.vol.ll
llvm.amdgcn.class.f16.ll
llvm.amdgcn.class.ll
llvm.amdgcn.cos.f16.ll
llvm.amdgcn.cos.ll
llvm.amdgcn.cubeid.ll
llvm.amdgcn.cubema.ll
llvm.amdgcn.cubesc.ll
llvm.amdgcn.cubetc.ll
llvm.amdgcn.cvt.pk.i16.ll
llvm.amdgcn.cvt.pk.u16.ll
llvm.amdgcn.cvt.pknorm.i16.ll
llvm.amdgcn.cvt.pknorm.u16.ll
llvm.amdgcn.cvt.pkrtz.ll
llvm.amdgcn.dispatch.id.ll
llvm.amdgcn.dispatch.ptr.ll
llvm.amdgcn.div.fixup.f16.ll
llvm.amdgcn.div.fixup.ll
llvm.amdgcn.div.fmas.ll
llvm.amdgcn.div.scale.ll
llvm.amdgcn.ds.append.ll
llvm.amdgcn.ds.bpermute.ll
llvm.amdgcn.ds.consume.ll
llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
llvm.amdgcn.ds.gws.barrier.ll [AMDGPU] Revise handling of preexisting waitcnt 2021-05-05 17:21:33 -07:00
llvm.amdgcn.ds.gws.init.ll
llvm.amdgcn.ds.gws.sema.br.ll
llvm.amdgcn.ds.gws.sema.p.ll
llvm.amdgcn.ds.gws.sema.release.all.ll
llvm.amdgcn.ds.gws.sema.v.ll
llvm.amdgcn.ds.ordered.add.gfx10.ll
llvm.amdgcn.ds.ordered.add.ll
llvm.amdgcn.ds.ordered.swap.ll
llvm.amdgcn.ds.permute.ll
llvm.amdgcn.ds.swizzle.ll
llvm.amdgcn.exp.compr.ll
llvm.amdgcn.exp.ll
llvm.amdgcn.exp.prim.ll
llvm.amdgcn.fcmp.ll
llvm.amdgcn.fdiv.fast.ll
llvm.amdgcn.fdot2.ll
llvm.amdgcn.fma.legacy.ll
llvm.amdgcn.fmad.ftz.f16.ll
llvm.amdgcn.fmad.ftz.ll
llvm.amdgcn.fmed3.f16.ll
llvm.amdgcn.fmed3.ll
llvm.amdgcn.fmul.legacy.ll
llvm.amdgcn.fract.f16.ll
llvm.amdgcn.fract.ll
llvm.amdgcn.frexp.exp.f16.ll
llvm.amdgcn.frexp.exp.ll
llvm.amdgcn.frexp.mant.f16.ll
llvm.amdgcn.frexp.mant.ll
llvm.amdgcn.groupstaticsize.ll
llvm.amdgcn.icmp.ll
llvm.amdgcn.image.a16.dim.ll
llvm.amdgcn.image.a16.encode.ll
llvm.amdgcn.image.atomic.dim.ll
llvm.amdgcn.image.d16.dim.ll
llvm.amdgcn.image.dim.gfx90a.ll
llvm.amdgcn.image.dim.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
llvm.amdgcn.image.gather4.a16.dim.ll
llvm.amdgcn.image.gather4.d16.dim.ll
llvm.amdgcn.image.gather4.dim.ll
llvm.amdgcn.image.gather4.o.dim.ll
llvm.amdgcn.image.getlod.dim.ll
llvm.amdgcn.image.load.a16.d16.ll
llvm.amdgcn.image.load.a16.ll
llvm.amdgcn.image.msaa.load.x.ll
llvm.amdgcn.image.nsa.ll
llvm.amdgcn.image.sample.a16.dim.ll [AMDGPU] Fix codegen of image intrinsics for g16 and a16 2021-05-14 09:28:15 +01:00
llvm.amdgcn.image.sample.d16.dim.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
llvm.amdgcn.image.sample.dim.gfx90a.ll
llvm.amdgcn.image.sample.dim.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
llvm.amdgcn.image.sample.g16.a16.dim.ll [AMDGPU] Fix codegen of image intrinsics for g16 and a16 2021-05-14 09:28:15 +01:00
llvm.amdgcn.image.sample.g16.encode.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
llvm.amdgcn.image.sample.g16.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
llvm.amdgcn.image.sample.ltolz.ll
llvm.amdgcn.image.sample.o.dim.ll
llvm.amdgcn.image.store.a16.d16.ll
llvm.amdgcn.image.store.a16.ll
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
llvm.amdgcn.implicit.buffer.ptr.ll
llvm.amdgcn.implicitarg.ptr.ll
llvm.amdgcn.init.exec.ll
llvm.amdgcn.init.exec.wave32.ll
llvm.amdgcn.interp.f16.ll
llvm.amdgcn.interp.ll
llvm.amdgcn.intersect_ray.ll
llvm.amdgcn.is.private.ll
llvm.amdgcn.is.shared.ll
llvm.amdgcn.kernarg.segment.ptr.ll
llvm.amdgcn.kill.ll
llvm.amdgcn.ldexp.f16.ll
llvm.amdgcn.ldexp.ll
llvm.amdgcn.lerp.ll
llvm.amdgcn.log.clamp.ll
llvm.amdgcn.mbcnt.ll
llvm.amdgcn.mfma.bf16.ll
llvm.amdgcn.mfma.gfx90a.ll
llvm.amdgcn.mfma.i8.ll
llvm.amdgcn.mfma.ll
llvm.amdgcn.mov.dpp8.ll
llvm.amdgcn.mov.dpp.ll
llvm.amdgcn.mqsad.pk.u16.u8.ll
llvm.amdgcn.mqsad.u32.u8.ll
llvm.amdgcn.msad.u8.ll
llvm.amdgcn.mul.i24.ll
llvm.amdgcn.mul.u24.ll
llvm.amdgcn.perm.ll [AMDGPU] Expose __builtin_amdgcn_perm for v_perm_b32 2021-05-06 16:17:33 -07:00
llvm.amdgcn.permlane.ll
llvm.amdgcn.ps.live.ll
llvm.amdgcn.qsad.pk.u16.u8.ll
llvm.amdgcn.queue.ptr.ll
llvm.amdgcn.raw.buffer.atomic.fadd.ll
llvm.amdgcn.raw.buffer.atomic.ll
llvm.amdgcn.raw.buffer.load.format.d16.ll
llvm.amdgcn.raw.buffer.load.format.ll
llvm.amdgcn.raw.buffer.load.ll
llvm.amdgcn.raw.buffer.store.format.d16.ll
llvm.amdgcn.raw.buffer.store.format.ll
llvm.amdgcn.raw.buffer.store.ll
llvm.amdgcn.raw.tbuffer.load.d16.ll
llvm.amdgcn.raw.tbuffer.load.ll [AMDGPU] getMemOperandsWithOffset: add vaddr operand for stack access BUF instructions 2021-05-14 10:10:43 +01:00
llvm.amdgcn.raw.tbuffer.store.d16.ll
llvm.amdgcn.raw.tbuffer.store.ll
llvm.amdgcn.rcp.f16.ll
llvm.amdgcn.rcp.legacy.ll
llvm.amdgcn.rcp.ll
llvm.amdgcn.readfirstlane.ll
llvm.amdgcn.readlane.ll
llvm.amdgcn.rsq.clamp.ll
llvm.amdgcn.rsq.f16.ll
llvm.amdgcn.rsq.legacy.ll
llvm.amdgcn.rsq.ll
llvm.amdgcn.s.barrier.ll
llvm.amdgcn.s.buffer.load.ll
llvm.amdgcn.s.dcache.inv.ll
llvm.amdgcn.s.dcache.inv.vol.ll
llvm.amdgcn.s.dcache.wb.ll
llvm.amdgcn.s.dcache.wb.vol.ll
llvm.amdgcn.s.decperflevel.ll
llvm.amdgcn.s.get.waveid.in.workgroup.ll
llvm.amdgcn.s.getpc.ll
llvm.amdgcn.s.getreg.ll
llvm.amdgcn.s.incperflevel.ll
llvm.amdgcn.s.memrealtime.ll
llvm.amdgcn.s.memtime.ll
llvm.amdgcn.s.sethalt.ll
llvm.amdgcn.s.setreg.ll
llvm.amdgcn.s.sleep.ll
llvm.amdgcn.s.waitcnt.ll
llvm.amdgcn.sad.hi.u8.ll
llvm.amdgcn.sad.u8.ll
llvm.amdgcn.sad.u16.ll
llvm.amdgcn.sbfe.ll
llvm.amdgcn.sdot2.ll
llvm.amdgcn.sdot4.ll
llvm.amdgcn.sdot8.ll
llvm.amdgcn.sendmsg.ll
llvm.amdgcn.set.inactive.ll
llvm.amdgcn.sffbh.ll
llvm.amdgcn.sin.f16.ll
llvm.amdgcn.sin.ll
llvm.amdgcn.softwqm.ll
llvm.amdgcn.sqrt.f16.ll
llvm.amdgcn.sqrt.ll
llvm.amdgcn.struct.buffer.atomic.fadd.ll
llvm.amdgcn.struct.buffer.atomic.ll
llvm.amdgcn.struct.buffer.load.format.d16.ll
llvm.amdgcn.struct.buffer.load.format.ll
llvm.amdgcn.struct.buffer.load.ll
llvm.amdgcn.struct.buffer.store.format.d16.ll
llvm.amdgcn.struct.buffer.store.format.ll
llvm.amdgcn.struct.buffer.store.ll
llvm.amdgcn.struct.tbuffer.load.d16.ll
llvm.amdgcn.struct.tbuffer.load.ll [AMDGPU] getMemOperandsWithOffset: add vaddr operand for stack access BUF instructions 2021-05-14 10:10:43 +01:00
llvm.amdgcn.struct.tbuffer.store.d16.ll
llvm.amdgcn.struct.tbuffer.store.ll
llvm.amdgcn.tbuffer.load.d16.ll
llvm.amdgcn.tbuffer.load.dwordx3.ll
llvm.amdgcn.tbuffer.load.ll [AMDGPU] getMemOperandsWithOffset: add vaddr operand for stack access BUF instructions 2021-05-14 10:10:43 +01:00
llvm.amdgcn.tbuffer.store.d16.ll
llvm.amdgcn.tbuffer.store.dwordx3.ll
llvm.amdgcn.tbuffer.store.ll
llvm.amdgcn.trig.preop.ll
llvm.amdgcn.ubfe.ll
llvm.amdgcn.udot2.ll
llvm.amdgcn.udot4.ll
llvm.amdgcn.udot8.ll
llvm.amdgcn.unreachable.ll
llvm.amdgcn.update.dpp.ll
llvm.amdgcn.wave.barrier.ll
llvm.amdgcn.wavefrontsize.ll
llvm.amdgcn.workgroup.id.ll
llvm.amdgcn.workitem.id.ll
llvm.amdgcn.wqm.demote.ll [AMDGPU] Fix WQM failure with single block inactive demote 2021-05-06 21:02:26 +09:00
llvm.amdgcn.wqm.vote.ll
llvm.amdgcn.writelane.ll
llvm.ceil.f16.ll
llvm.cos.f16.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
llvm.cos.ll
llvm.dbg.value.ll
llvm.exp2.f16.ll
llvm.exp2.ll
llvm.floor.f16.ll
llvm.fma.f16.ll
llvm.fmuladd.f16.ll
llvm.log2.f16.ll
llvm.log2.ll
llvm.log10.f16.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
llvm.log10.ll
llvm.log.f16.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
llvm.log.ll
llvm.maxnum.f16.ll
llvm.memcpy.ll
llvm.minnum.f16.ll
llvm.mulo.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
llvm.pow-gfx9.ll
llvm.pow.ll
llvm.powi.ll
llvm.r600.cube.ll
llvm.r600.dot4.ll
llvm.r600.group.barrier.ll
llvm.r600.read.local.size.ll
llvm.r600.recipsqrt.clamped.ll
llvm.r600.recipsqrt.ieee.ll
llvm.r600.tex.ll
llvm.rint.f16.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
llvm.rint.f64.ll
llvm.rint.ll
llvm.round.f64.ll
llvm.round.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
llvm.sin.f16.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
llvm.sin.ll
llvm.sqrt.f16.ll
llvm.trunc.f16.ll
lo16-32bit-physreg-copy.mir
lo16-hi16-illegal-copy.mir
lo16-hi16-physreg-copy.mir
lo16-lo16-physreg-copy-agpr.mir
lo16-lo16-physreg-copy-sgpr.mir
load-constant-f32.ll
load-constant-f64.ll
load-constant-i1.ll
load-constant-i8.ll
load-constant-i16.ll
load-constant-i32.ll
load-constant-i64.ll
load-global-f32.ll
load-global-f64.ll
load-global-i1.ll
load-global-i8.ll
load-global-i16.ll
load-global-i32.ll
load-global-i64.ll
load-hi16.ll
load-input-fold.ll
load-lo16.ll
load-local-f32-no-ds128.ll
load-local-f32.ll
load-local-f64.ll
load-local-i1.ll
load-local-i8.ll
load-local-i16.ll
load-local-i32.ll
load-local-i64.ll
load-local-redundant-copies.ll
load-local.96.ll
load-local.128.ll
load-select-ptr.ll
load-weird-sizes.ll
local-64.ll
local-atomics64.ll
local-atomics-fp.ll
local-atomics.ll
local-memory.amdgcn.ll
local-memory.ll
local-memory.r600.ll
local-stack-alloc-block-sp-reference.ll [AMDGPU] Restrict immediate scratch offsets 2021-05-07 14:51:32 +02:00
local-stack-slot-offset.ll
loop_break.ll
loop_exit_with_xor.ll [AMDGPU] Move code sinking before structurizer 2021-05-11 14:07:23 +02:00
loop_header_nopred.mir
loop-address.ll
loop-idiom.ll
loop-live-out-copy-undef-subrange.ll
loop-prefetch.ll
lower-control-flow-other-terminators.mir
lower-kernargs.ll
lower-mem-intrinsics-threshold.ll
lower-mem-intrinsics.ll
lower-module-lds-constantexpr.ll [AMDGPU] Fix module LDS selection 2021-05-20 15:59:01 -07:00
lower-module-lds-inactive.ll
lower-module-lds-indirect.ll [AMDGPU] Fix module LDS selection 2021-05-20 15:59:01 -07:00
lower-module-lds-offsets.ll [AMDGPU] Fix module LDS selection 2021-05-20 15:59:01 -07:00
lower-module-lds-used-list.ll [AMDGPU] Fix module LDS selection 2021-05-20 15:59:01 -07:00
lower-module-lds.ll [AMDGPU] Fix module LDS selection 2021-05-20 15:59:01 -07:00
lower-range-metadata-intrinsic-call.ll
lower-term-opcodes.mir
lshl64-to-32.ll
lshr.v2i16.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
machine-cse-commute-target-flags.mir
machinelicm-convergent.mir
macro-fusion-cluster-vcc-uses.mir
mad24-get-global-id.ll
mad_64_32.ll
mad_int24.ll
mad_uint24.ll
mad-combine.ll
mad-mix-hi.ll
mad-mix-lo.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
mad-mix.ll
mad.u16.ll
madak-inline-constant.mir
madak.ll
madmk.ll
mai-hazards-gfx90a.mir
mai-hazards.mir
mai-inline.ll
max3.ll
max-literals.ll
max-sgprs.ll
max.i16.ll
max.ll
mcp-overlap-after-propagation.mir
med3-no-simplify.ll
mem-builtins.ll
memcpy-fixed-align.ll
memcpy-inline-fails.ll
memory_clause.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
memory_clause.mir
memory-legalizer-atomic-insert-end.mir
memory-legalizer-fence.ll
memory-legalizer-flat-agent.ll [AMDGPU] Revise handling of preexisting waitcnt 2021-05-05 17:21:33 -07:00
memory-legalizer-flat-nontemporal.ll
memory-legalizer-flat-singlethread.ll
memory-legalizer-flat-system.ll [AMDGPU] Revise handling of preexisting waitcnt 2021-05-05 17:21:33 -07:00
memory-legalizer-flat-volatile.ll [AMDGPU] Revise handling of preexisting waitcnt 2021-05-05 17:21:33 -07:00
memory-legalizer-flat-wavefront.ll
memory-legalizer-flat-workgroup.ll [AMDGPU] Revise handling of preexisting waitcnt 2021-05-05 17:21:33 -07:00
memory-legalizer-global-agent.ll
memory-legalizer-global-nontemporal.ll
memory-legalizer-global-singlethread.ll
memory-legalizer-global-system.ll
memory-legalizer-global-volatile.ll
memory-legalizer-global-wavefront.ll
memory-legalizer-global-workgroup.ll
memory-legalizer-invalid-addrspace.mir
memory-legalizer-invalid-syncscope.ll
memory-legalizer-local-agent.ll
memory-legalizer-local-nontemporal.ll
memory-legalizer-local-singlethread.ll
memory-legalizer-local-system.ll
memory-legalizer-local-volatile.ll
memory-legalizer-local-wavefront.ll
memory-legalizer-local-workgroup.ll
memory-legalizer-local.mir
memory-legalizer-multiple-mem-operands-atomics.mir
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
memory-legalizer-private-nontemporal.ll
memory-legalizer-private-volatile.ll
memory-legalizer-region.mir
memory-legalizer-store-infinite-loop.ll
merge-image-load-gfx10.mir
merge-image-load.mir
merge-image-sample-gfx10.mir
merge-image-sample.mir
merge-load-store-agpr.mir
merge-load-store-physreg.mir
merge-load-store-vreg.mir
merge-load-store.mir
merge-m0.mir
merge-out-of-order-ldst.ll
merge-out-of-order-ldst.mir
merge-store-crash.ll
merge-store-usedef.ll
merge-stores.ll
merge-tbuffer.mir
mesa3d.ll
mesa_regression.ll
mfma-loop.ll
min3.ll
min.ll
mir-print-dead-csr-fi.mir
misched-killflags.mir
missing-store.ll
mixed_wave32_wave64.ll
mixed-wave32-wave64.ll
mode-register.mir
move-addr64-rsrc-dead-subreg-writes.ll
move-load-addr-to-valu.mir [AMDGPU] Change FLAT Scratch SADDR to VADDR form in moveToVALU 2021-05-03 10:57:14 -07:00
move-to-valu-atomicrmw.ll
move-to-valu-worklist.ll
movreld-bug.ll
movrels-bug.mir
mubuf-legalize-operands.ll
mubuf-legalize-operands.mir
mubuf-offset-private.ll
mubuf-shader-vgpr.ll
mubuf.ll
mul24-pass-ordering.ll [AMDGPU] Skip invariant loads when avoiding WAR conflicts 2021-05-12 10:57:05 +02:00
mul_int24.ll
mul_uint24-amdgcn.ll
mul_uint24-r600.ll
mul.i16.ll
mul.ll
multi-divergent-exit-region.ll
multi-dword-vgpr-spill.ll
multilevel-break.ll [AMDGPU] Move code sinking before structurizer 2021-05-11 14:07:23 +02:00
nand.ll
need-fp-from-csr-vgpr-spill.ll
nested-calls.ll
nested-loop-conditions.ll
no-bundle-asm.ll
no-hsa-graphics-shaders.ll
no-initializer-constant-addrspace.ll
no-remat-indirect-mov.mir
no-shrink-extloads.ll
non-entry-alloca.ll
noop-shader-O0.ll
nop-data.ll
nor.ll
not-scalarize-volatile-load.ll
nsa-reassign.ll
nsa-reassign.mir
nsa-vmem-hazard.mir
nullptr.ll
occupancy-levels.ll
offset-split-flat.ll
offset-split-global.ll [AMDGPU] Improve global SADDR selection 2021-05-05 14:44:21 -07:00
omod-nsz-flag.mir
omod.ll
opencl-image-metadata.ll
opencl-printf-no-hostcall.ll
opencl-printf.ll
operand-folding.ll
operand-spacing.ll
opt_exec_copy_fold.mir
opt-pipeline.ll [VectorCombine] Simplify to scalar store if only one element updated 2021-05-08 18:14:51 +08:00
opt-sgpr-to-vgpr-copy.mir
optimize-exec-copies-extra-insts-after-copy.mir
optimize-exec-mask-pre-ra-loop-phi.mir
optimize-exec-masking-pre-ra.mir
optimize-exec-masking-strip-terminator-bits.mir
optimize-if-exec-masking.mir
optimize-negated-cond-exec-masking-wave32.mir
optimize-negated-cond-exec-masking.mir
optimize-negated-cond.ll
or3.ll
or.ll
pack.v2f16.ll
pack.v2i16.ll
packed-fp32.ll
packed-op-sel.ll
packetizer.ll
pal-simple-indirect-call.ll AMDGPU: Correct const_index_stride for wave 32 for PAL ABI 2021-05-07 13:42:57 +01:00
pal-userdata-regs.ll
parallelandifcollapse.ll
parallelorifcollapse.ll
partial-sgpr-to-vgpr-spills.ll
partial-shift-shrink.ll
partially-dead-super-register-immediate.ll
peephole-opt-regseq-removal.mir
pei-build-spill-partial-agpr.mir [AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks 2021-04-30 14:10:50 +01:00
pei-build-spill.mir
pei-reg-scavenger-position.mir
pei-scavenge-sgpr-carry-out.mir
pei-scavenge-sgpr-gfx9.mir
pei-scavenge-sgpr.mir
pei-scavenge-vgpr-spill.mir
perfhint.ll
permute.ll
phi-elimination-assertion.mir
phi-elimination-end-cf.mir
phi-vgpr-input-moveimm.mir
pk_max_f16_literal.ll
post-ra-sched-kill-bundle-use-inst.mir
post-ra-sched-reset.mir
post-ra-soft-clause-dbg-info.ll
postra-bundle-memops.mir
postra-machine-sink.mir
postra-norename.mir
power-sched-no-instr-sunit.mir
predicate-dp4.ll
predicates.ll
preserve-hi16.ll
print-mir-custom-pseudo.ll
private-access-no-objects.ll
private-element-size.ll
private-memory-atomics.ll
private-memory-r600.ll
promote-alloca-addrspacecast.ll
promote-alloca-array-aggregate.ll
promote-alloca-array-allocation.ll
promote-alloca-bitcast-function.ll
promote-alloca-calling-conv.ll
promote-alloca-globals.ll
promote-alloca-invariant-markers.ll
promote-alloca-lifetime.ll
promote-alloca-mem-intrinsics.ll
promote-alloca-no-opts.ll
promote-alloca-padding-size-estimate.ll
promote-alloca-pointer-array.ll
promote-alloca-stored-pointer-value.ll
promote-alloca-to-lds-constantexpr-use.ll
promote-alloca-to-lds-icmp.ll
promote-alloca-to-lds-phi.ll
promote-alloca-to-lds-select.ll
promote-alloca-unhandled-intrinsic.ll
promote-alloca-vector-to-vector.ll
promote-alloca-volatile.ll
promote-constOffset-to-imm-gfx10.mir
promote-constOffset-to-imm-gfx90a.mir AMDGPU: Fix SILoadStoreOptimizer for gfx90a 2021-05-11 21:26:43 -04:00
promote-constOffset-to-imm.ll AMDGPU: Fix SILoadStoreOptimizer for gfx90a 2021-05-11 21:26:43 -04:00
promote-constOffset-to-imm.mir
promote-vect3-load.ll
propagate-attributes-bitcast-function.ll
propagate-attributes-clone.ll
propagate-attributes-flat-work-group-size.ll
propagate-attributes-single-set.ll
ptr-arg-dbg-value.ll [MCAsmInfo] Support UsesCFIForDebug for targets with no exception handling 2021-05-06 04:53:45 +05:30
ptrmask.ll
pv-packing.ll
pv.ll
r600-constant-array-fixup.ll
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600-legalize-umax-bug.ll
r600.add.ll
r600.alu-limits.ll
r600.amdgpu-alias-analysis.ll
r600.bitcast.ll
r600.extract-lowbits.ll
r600.func-alignment.ll
r600.global_atomics.ll
r600.private-memory.ll
r600.sub.ll
r600.work-item-intrinsics.ll
r600cfg.ll
rcp_iflag.ll
rcp-pattern.ll
read_register.ll
read-register-invalid-subtarget.ll
read-register-invalid-type-i32.ll
read-register-invalid-type-i64.ll
readcyclecounter.ll [AMDGPU] Add some GFX10.3 testing. NFC. 2021-05-11 11:21:19 +01:00
readlane_exec0.mir
README
reassoc-scalar.ll
reduce-build-vec-ext-to-ext-build-vec.ll
reduce-load-width-alignment.ll
reduce-saveexec.mir
reduce-store-width-alignment.ll
reduction.ll
reg-coalescer-sched-crash.ll
regcoal-subrange-join-seg.mir
regcoal-subrange-join.mir
regcoalesce-cannot-join-failures.mir
regcoalesce-dbg.mir
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
regcoalesce-prune.mir
regcoalescing-remove-partial-redundancy-assert.mir
register-count-comments.ll
rel32.ll
remove-short-exec-branches-gpr-idx-mode.mir
remove-short-exec-branches-special-instructions.mir
rename-disconnected-bug.ll
rename-independent-subregs-mac-operands.mir
rename-independent-subregs.mir
reorder-stores.ll
reqd-work-group-size.ll
reserve-vgpr-for-sgpr-spill.ll
reserved-reg-in-clause.mir
ret_jump.ll
ret.ll
return-with-successors.mir
returnaddress.ll
rewrite-out-arguments-address-space.ll
rewrite-out-arguments.ll
rotl.i64.ll
rotl.ll
rotr.i64.ll
rotr.ll
rsq.ll
rv7x0_count3.ll
s_add_co_pseudo_lowering.mir
s_addk_i32.ll
s_code_end.ll
s_movk_i32.ll
s_mulk_i32.ll
sad.ll
saddo.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
saddsat.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
salu-to-valu.ll [AMDGPU] getMemOperandsWithOffset: add vaddr operand for stack access BUF instructions 2021-05-14 10:10:43 +01:00
sampler-resource-id.ll
scalar_to_vector_v2x16.ll
scalar_to_vector.ll
scalar-branch-missing-and-exec.ll
scalar-store-cache-flush.mir
sched-assert-dead-def-subreg-use-other-subreg.mir
sched-assert-onlydbg-value-empty-region.mir
sched-crash-dbg-value.mir
sched-handleMoveUp-subreg-def-across-subreg-def.mir
sched-prefer-non-mfma.mir
schedule-barrier-fpmode.mir
schedule-barrier.mir
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-global-loads.ll
schedule-if-2.ll
schedule-if.ll
schedule-ilp.ll
schedule-kernel-arg-loads.ll
schedule-regpressure-limit2.ll
schedule-regpressure-limit3.ll
schedule-regpressure-limit-clustering.ll
schedule-regpressure-limit.ll
schedule-regpressure.mir
schedule-vs-if-nested-loop-failure.ll
schedule-vs-if-nested-loop.ll
schedule-xdl-resource.ll
scheduler-handle-move-bundle.mir
scheduler-subrange-crash.ll
scratch-buffer.ll
scratch-simple.ll
sdiv64.ll [AMDGPU] Update SCC defs to VCC when uses are changed to VCC 2021-05-14 18:05:05 -04:00
sdiv.ll
sdivrem24.ll
sdivrem64.r600.ll
sdwa-gfx9.mir
sdwa-op64-test.ll
sdwa-ops.mir
sdwa-peephole-instr-gfx10.mir
sdwa-peephole-instr.mir
sdwa-peephole.ll
sdwa-preserve.mir
sdwa-scalar-ops.mir
sdwa-stack.mir
sdwa-vop2-64bit.mir
select64.ll
select-constant-cttz.ll
select-fabs-fneg-extract-legacy.ll
select-fabs-fneg-extract.ll
select-i1.ll
select-opt.ll
select-undef.ll
select-vectors.ll
select.f16.ll
select.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll
selectcc.ll
sendmsg-m0-hazard.mir
set-dx10.ll
set-gpr-idx-peephole.mir [AMDGPU] Remove set_gpr_idx instructions in conditional blocks 2021-04-30 22:15:45 +01:00
setcc64.ll
setcc-equivalent.ll
setcc-fneg-constant.ll
setcc-limit-load-shrink.ll
setcc-opt.ll
setcc-sext.ll
setcc.ll
seto.ll
setuo.ll
sext-divergence-driven-isel.ll
sext-eliminate.ll
sext-in-reg-failure-r600.ll
sext-in-reg.ll
sgpr-control-flow.ll
sgpr-copy-duplicate-operand.ll
sgpr-copy-local-cse.ll
sgpr-copy.ll
sgpr-phys-copy.mir
sgpr-spill-dead-frame-in-dbg-value.mir
sgpr-spill-partially-undef.mir
sgpr-spill-wrong-stack-id.mir
sgpr-spill.mir [AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks 2021-04-30 14:10:50 +01:00
sgprcopies.ll
shader-addr64-nonuniform.ll
shared-op-cycle.ll
shift-and-i64-ubfe.ll
shift-and-i128-ubfe.ll
shift-i64-opts.ll
shift-i128.ll
shift-select.ll
shl_add_constant.ll
shl_add_ptr_csub.ll
shl_add_ptr_global.ll
shl_add_ptr.ll
shl_add.ll
shl_or.ll
shl-add-to-add-shl.ll
shl.ll [DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts 2021-05-07 13:12:30 +01:00
shl.v2i16.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
shrink-add-sub-constant.ll
shrink-carry.mir
shrink-instructions-flags.mir
shrink-instructions-illegal-fold.mir
shrink-instructions-implicit-vcclo.mir
shrink-insts-scalar-bit-ops.mir
shrink-vop3-carry-out.mir
si-annotate-cf-kill.ll
si-annotate-cf-noloop.ll
si-annotate-cf-unreachable.ll
si-annotate-cf.ll
si-annotate-cfg-loop-assert.ll
si-annotatecfg-multiple-backedges.ll
si-fix-sgpr-copies.mir
si-i1-copies.mir
si-instr-info-correct-implicit-operands.ll
si-lower-control-flow-kill.ll
si-lower-control-flow-unreachable-block.ll
si-lower-control-flow.mir
si-lower-i1-copies.mir
si-lower-sgpr-spills.mir
si-scheduler.ll
si-sgpr-spill.ll
si-spill-cf.ll
si-spill-sgpr-stack.ll
si-triv-disjoint-mem-access.ll
si-vector-hang.ll
sibling-call.ll AMDGPU: Fix lit test 2021-05-05 18:41:18 -04:00
sign_extend.ll
simple-indirect-call.ll
simplify-libcalls2.ll
simplify-libcalls.ll
simplifydemandedbits-recursion.ll
sink-image-sample.ll [AMDGPU] Move code sinking before structurizer 2021-05-11 14:07:23 +02:00
sint_to_fp.f64.ll
sint_to_fp.i64.ll
sint_to_fp.ll
sitofp.f16.ll
skip-branch-taildup-ret.mir
skip-branch-trap.ll
skip-if-dead.ll
skip-promote-alloca-vector-users.ll [AMDGPU] Skip promote-alloca for insertelement/insertvalue users 2021-04-30 08:37:26 +05:30
smed3.ll
smem-no-clause-coalesced.mir
smem-war-hazard.mir
sminmax.ll
sminmax.v2i16.ll
smrd_vmem_war.ll
smrd-fold-offset.mir
smrd-gfx10.ll
smrd-vccz-bug.ll
smrd.ll
soft-clause-dbg-value.mir
soft-clause-exceeds-register-budget.ll [AMDGPU] Switch AnnotateUniformValues to MemorySSA 2021-05-05 18:34:41 -07:00
sopk-compares.ll
speculative-execution-freecasts.ll
spill192.mir
spill_more_than_wavesize_csr_sgprs.ll
spill-agpr-partially-undef.mir
spill-agpr.ll
spill-agpr.mir
spill-alloc-sgpr-init-bug.ll
spill-before-exec.mir
spill-cfg-position.ll
spill-csr-frame-ptr-reg-copy.ll
spill-empty-live-interval.mir
spill-m0.ll
spill-offset-calculation.ll
spill-reg-tuple-super-reg-use.mir
spill-scavenge-offset.ll
spill-sgpr-csr-live-ins.mir
spill-sgpr-stack-no-sgpr.ll
spill-special-sgpr.mir
spill-vgpr-to-agpr.ll
spill-wide-sgpr.ll
split-arg-dbg-value.ll [MCAsmInfo] Support UsesCFIForDebug for targets with no exception handling 2021-05-06 04:53:45 +05:30
split-scalar-i64-add.ll
split-smrd.ll
split-vector-memoperand-offsets.ll
splitkit-copy-bundle.mir
splitkit-copy-live-lanes.mir
splitkit-getsubrangeformask.ll
splitkit-nolivesubranges.mir
splitkit.mir
sra.ll [DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts 2021-05-07 13:12:30 +01:00
sram-ecc-default.ll
sramecc-subtarget-feature-any.ll
sramecc-subtarget-feature-disabled.ll
sramecc-subtarget-feature-enabled.ll
srem64.ll [AMDGPU] Update SCC defs to VCC when uses are changed to VCC 2021-05-14 18:05:05 -04:00
srem-seteq-illegal-types.ll
srem.ll
srl.ll [DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts 2021-05-07 13:12:30 +01:00
sroa-before-unroll.ll
SRSRC-GIT-clobber-check.mir
ssubo.ll
ssubsat.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
stack-pointer-offset-relative-frameindex.ll
stack-realign-kernel.ll
stack-realign.ll [AMDGPU] Skip invariant loads when avoiding WAR conflicts 2021-05-12 10:57:05 +02:00
stack-size-overflow.ll
stack-slot-color-sgpr-vgpr-spills.mir
stale-livevar-in-twoaddr-pass.mir
store_typed.ll
store-barrier.ll
store-clobbers-load.ll
store-global.ll
store-hi16.ll
store-local.96.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
store-local.128.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
store-local.ll
store-private.ll
store-v3i64.ll
store-vector-ptrs.ll
store-weird-sizes.ll
stress-calls.ll
strict_fadd.f16.ll
strict_fadd.f32.ll
strict_fadd.f64.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
strict_fma.f16.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
strict_fma.f32.ll
strict_fma.f64.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
strict_fmul.f16.ll
strict_fmul.f32.ll
strict_fmul.f64.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
strict_fsub.f16.ll
strict_fsub.f32.ll
strict_fsub.f64.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
structurize1.ll
structurize.ll
sub_i1.ll
sub-zext-cc-zext-cc.ll
sub.i16.ll
sub.ll
sub.v2i16.ll
subreg_interference.mir
subreg-coalescer-crash.ll
subreg-coalescer-undef-use.ll
subreg-eliminate-dead.ll
subreg-intervals.mir
subreg-split-live-in-error.mir
subreg-undef-def-with-other-subreg-defs.mir
subvector-test.mir
swdev282079.ll
swdev282079.mir
switch-default-block-unreachable.ll
switch-unreachable.ll
swizzle-export.ll
syncscopes.ll
tail-call-amdgpu-gfx.ll [TargetLowering] Only inspect attributes in the arguments for ArgListEntry 2021-05-18 14:30:22 -07:00
tail-call-cgp.ll
tail-dup-bundle.mir
tail-duplication-convergent.ll
target-cpu.ll
tex-clause-antidep.ll
texture-input-merge.ll
tgsplit.ll
tid-code-object-v2-backwards-compatibility.ll
tid-mul-func-xnack-all-any.ll
tid-mul-func-xnack-all-not-supported.ll
tid-mul-func-xnack-all-off.ll
tid-mul-func-xnack-all-on.ll
tid-mul-func-xnack-any-off-1.ll
tid-mul-func-xnack-any-off-2.ll
tid-mul-func-xnack-any-on-1.ll
tid-mul-func-xnack-any-on-2.ll
tid-mul-func-xnack-invalid-any-off-on.ll
tid-one-func-xnack-any.ll
tid-one-func-xnack-not-supported.ll
tid-one-func-xnack-off.ll
tid-one-func-xnack-on.ll
token-factor-inline-limit-test.ll
transform-block-with-return-to-epilog.ll
trap-abis.ll
trap.ll
trunc-bitcast-vector.ll
trunc-cmp-constant.ll
trunc-combine.ll
trunc-store-f64-to-f16.ll
trunc-store-i1.ll
trunc-store-i64.ll
trunc-store-vec-i16-to-i8.ll
trunc-store.ll
trunc-vector-store-assertion-failure.ll
trunc.ll
tti-unroll-prefs.ll
twoaddr-fma-f64.mir
twoaddr-fma.mir
twoaddr-mad.mir
uaddo.ll
uaddsat.ll
udiv64.ll [AMDGPU] Update SCC defs to VCC when uses are changed to VCC 2021-05-14 18:05:05 -04:00
udiv.ll
udivrem24.ll
udivrem64.r600.ll
udivrem.ll
uint_to_fp.f64.ll
uint_to_fp.i64.ll
uint_to_fp.ll
uitofp.f16.ll
umed3.ll
unaligned-load-store.ll
unallocatable-bundle-regression.mir
undef-subreg-use-after-coalesce.mir
undefined-physreg-sgpr-spill.mir
undefined-subreg-liverange.ll
unexpected-reg-unit-state.mir
unhandled-loop-condition-assertion.ll
uniform-branch-intrinsic-cond.ll
uniform-cfg.ll
uniform-crash.ll
uniform-loop-inside-nonuniform.ll
uniform-work-group-attribute-missing.ll
uniform-work-group-nested-function-calls.ll
uniform-work-group-prevent-attribute-propagation.ll
uniform-work-group-propagate-attribute.ll
uniform-work-group-recursion-test.ll
uniform-work-group-test.ll
unify-metadata.ll
unigine-liveness-crash.ll
unknown-processor.ll
unpack-half.ll
unroll.ll
unstructured-cfg-def-use-issue.ll
unsupported-calls.ll
unsupported-cc.ll
unsupported-image-a16.ll
unsupported-image-g16.ll
update-phi.ll
urem64.ll [AMDGPU] Update SCC defs to VCC when uses are changed to VCC 2021-05-14 18:05:05 -04:00
urem-seteq-illegal-types.ll
urem.ll
use-sgpr-multiple-times.ll
usubo.ll
usubsat.ll
v1i64-kernel-arg.ll
v1024.ll
v_cndmask.ll
v_cvt_pk_u8_f32.ll
v_mac_f16.ll
v_mac.ll
v_madak_f16.ll
v_mov_b64_expansion.mir
v_pack.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
v_swap_b32.mir [AMDGPU] Fix v_swap_b32 formation on physical registers 2021-04-29 20:53:40 +01:00
valu-i1.ll
vccz-corrupt-bug-workaround.mir
vcmpx-exec-war-hazard.mir
vcmpx-permlane-hazard.mir
vector_shuffle.packed.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
vector-alloca-addrspacecast.ll
vector-alloca-atomic.ll
vector-alloca-bitcast.ll
vector-alloca-limits.ll
vector-alloca.ll
vector-extract-insert.ll
vector-legalizer-divergence.ll
vectorize-buffer-fat-pointer.ll
vectorize-global-local.ll
vectorize-loads.ll
verify-constant-bus-violations.mir
verify-duplicate-literal.mir
verify-gfx90a-aligned-vgprs.mir
verify-sop.mir
vertex-fetch-encoding.ll
vgpr-descriptor-waterfall-loop-idom-update.ll
vgpr-remat.mir
vgpr-spill-dead-frame-in-dbg-value.mir
vgpr-spill-emergency-stack-slot-compute.ll
vgpr-spill-emergency-stack-slot.ll
vgpr-spill.mir
vgpr-tuple-allocation.ll
vi-removed-intrinsics.ll
virtregrewrite-undef-identity-copy.mir
visit-physreg-vgpr-imm-folding-bug.ll
vmem-to-salu-hazard.mir
vmem-vcc-hazard.mir
vop-shrink-frame-index.mir
vop-shrink-non-ssa.mir
vop-shrink.ll
vselect64.ll
vselect.ll
vtx-fetch-branch.ll
vtx-schedule.ll
wait.ll
waitcnt-agpr.mir
waitcnt-back-edge-loop.mir
waitcnt-debug.mir [AMDGPU] Revise handling of preexisting waitcnt 2021-05-05 17:21:33 -07:00
waitcnt-flat.ll
waitcnt-loop-irreducible.mir
waitcnt-loop-single-basic-block.mir
waitcnt-looptest.ll
waitcnt-meta-instructions.mir
waitcnt-no-redundant.mir [AMDGPU] Skip invariant loads when avoiding WAR conflicts 2021-05-12 10:57:05 +02:00
waitcnt-overflow.mir
waitcnt-permute.mir
waitcnt-preexisting-vscnt.mir [AMDGPU] Revise handling of preexisting waitcnt 2021-05-05 17:21:33 -07:00
waitcnt-preexisting.mir [AMDGPU] Fix extra waitcnt being added with BUFFER_INVL2 2021-05-11 13:17:33 -07:00
waitcnt-skip-meta.mir
waitcnt-vmem-waw.mir
waitcnt-vscnt.ll
waitcnt-vscnt.mir
waitcnt.mir
wave32.ll Revert rGd70cbd1ce9b426f2c7e0e0f900769bbcbb300a95 "[AMDGPU] Regenerate wave32.ll tests" 2021-05-18 12:15:38 +01:00
wave_dispatch_regs.ll
widen_extending_scalar_loads.ll
widen-smrd-loads.ll
widen-vselect-and-mask.ll
wqm.ll
wqm.mir
write_register.ll
write-register-vgpr-into-sgpr.ll
wrong-transalu-pos-fix.ll
wwm-reserved-spill.ll
wwm-reserved.ll
xfail.r600.bitcast.ll
xnack-subtarget-feature-any.ll
xnack-subtarget-feature-disabled.ll
xnack-subtarget-feature-enabled.ll
xnor.ll
xor3-i1-const.ll
xor3.ll
xor_add.ll
xor.ll
zero_extend.ll
zext-i64-bit-operand.ll
zext-lid.ll

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.