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c57b91da41
Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
113 lines
3.9 KiB
LLVM
113 lines
3.9 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -stress-early-ifcvt -amdgpu-early-ifcvt=1 -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -stress-early-ifcvt -amdgpu-early-ifcvt=1 -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCNX3 %s
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; FIXME: Most of these cases that don't trigger because of broken cost
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; heuristics. Should not need -stress-early-ifcvt
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; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle64:
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; GCN: buffer_load_dwordx2 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
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; GCN: v_cmp_neq_f64_e32 vcc, 1.0, v{{\[}}[[VAL_LO]]:[[VAL_HI]]{{\]}}
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; GCN: v_add_f64 v{{\[}}[[ADD_LO:[0-9]+]]:[[ADD_HI:[0-9]+]]{{\]}}, v{{\[}}[[VAL_LO]]:[[VAL_HI]]{{\]}}, v{{\[}}[[VAL_LO]]:[[VAL_HI]]{{\]}}
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; GCN-DAG: v_cndmask_b32_e32 v[[RESULT_LO:[0-9]+]], v[[ADD_LO]], v[[VAL_LO]], vcc
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; GCN-DAG: v_cndmask_b32_e32 v[[RESULT_HI:[0-9]+]], v[[ADD_HI]], v[[VAL_HI]], vcc
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; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}}
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define amdgpu_kernel void @test_vccnz_ifcvt_triangle64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
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entry:
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%v = load double, double addrspace(1)* %in
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%cc = fcmp oeq double %v, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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%u = fadd double %v, %v
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br label %endif
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endif:
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%r = phi double [ %v, %entry ], [ %u, %if ]
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store double %r, double addrspace(1)* %out
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ret void
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}
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; vcc branch with SGPR inputs
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; GCN-LABEL: {{^}}test_vccnz_sgpr_ifcvt_triangle64:
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; GCN: v_cmp_neq_f64
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; GCN: v_add_f64
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; GCN: v_cndmask_b32_e32
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; GCN: v_cndmask_b32_e32
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define amdgpu_kernel void @test_vccnz_sgpr_ifcvt_triangle64(double addrspace(1)* %out, double addrspace(4)* %in) #0 {
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entry:
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%v = load double, double addrspace(4)* %in
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%cc = fcmp oeq double %v, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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%u = fadd double %v, %v
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br label %endif
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endif:
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%r = phi double [ %v, %entry ], [ %u, %if ]
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store double %r, double addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle96:
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; GCN: v_cmp_neq_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 1.0
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: s_mov_b64 vcc, [[CMP]]
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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; SI-DAG: buffer_store_dwordx2
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; SI-DAG: buffer_store_dword v
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; GCNX3: buffer_store_dwordx3
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define amdgpu_kernel void @test_vccnz_ifcvt_triangle96(<3 x i32> addrspace(1)* %out, <3 x i32> addrspace(1)* %in, float %cnd) #0 {
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entry:
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%v = load <3 x i32>, <3 x i32> addrspace(1)* %in
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%cc = fcmp oeq float %cnd, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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%u = add <3 x i32> %v, %v
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br label %endif
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endif:
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%r = phi <3 x i32> [ %v, %entry ], [ %u, %if ]
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store <3 x i32> %r, <3 x i32> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle128:
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; GCN: v_cmp_neq_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 1.0
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: s_mov_b64 vcc, [[CMP]]
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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; GCN: buffer_store_dwordx4
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define amdgpu_kernel void @test_vccnz_ifcvt_triangle128(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in, float %cnd) #0 {
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entry:
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%v = load <4 x i32>, <4 x i32> addrspace(1)* %in
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%cc = fcmp oeq float %cnd, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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%u = add <4 x i32> %v, %v
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br label %endif
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endif:
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%r = phi <4 x i32> [ %v, %entry ], [ %u, %if ]
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store <4 x i32> %r, <4 x i32> addrspace(1)* %out
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ret void
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}
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