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llvm-mirror/test/CodeGen/AMDGPU/hazard-in-bundle.mir
Stanislav Mekhanoshin 196e7f3138 [AMDGPU] Use single cache policy operand
Replace individual operands GLC, SLC, and DLC with a single cache_policy
bitmask operand. This will reduce the number of operands in MIR and I hope
the amount of code. These operands are mostly 0 anyway.

Additional advantage that parser will accept these flags in any order unlike
now.

Differential Revision: https://reviews.llvm.org/D96469
2021-03-15 13:00:59 -07:00

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# RUN: llc -march=amdgcn -mcpu=gfx902 -mattr=+xnack -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,XNACK,GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-xnack -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK,GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64,-xnack -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK,GFX10 %s
# GCN-LABEL: name: break_smem_clause_max_look_ahead_in_bundle
# GCN: S_LOAD_DWORDX2_IMM
# XNACK-NEXT: S_NOP
# NOXNACK-NOT: S_NOP
# GCN: S_LOAD_DWORDX2
# XNACK-NEXT: S_NOP
# NOXNACK-NOT: S_NOP
# GCN: }
---
name: break_smem_clause_max_look_ahead_in_bundle
body: |
bb.0:
BUNDLE implicit-def $sgpr6_sgpr7 {
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0
S_STORE_DWORD_IMM $sgpr8, $sgpr10_sgpr11, 0, 0
S_STORE_DWORD_IMM $sgpr8, $sgpr10_sgpr11, 4, 0
S_STORE_DWORD_IMM $sgpr8, $sgpr10_sgpr11, 8, 0
S_STORE_DWORD_IMM $sgpr8, $sgpr10_sgpr11, 12, 0
S_STORE_DWORD_IMM $sgpr8, $sgpr10_sgpr11, 16, 0
$sgpr14_sgpr15 = S_LOAD_DWORDX2_IMM $sgpr12_sgpr13, 0, 0
$sgpr16_sgpr17 = S_LOAD_DWORDX2_IMM $sgpr14_sgpr15, 0, 0
}
S_ENDPGM 0
...
# GFX10-LABEL: name: hazard_smem_war_in_bundle
# GFX10: S_LOAD_DWORD_IMM
# GFX10-NEXT: $sgpr_null = S_MOV_B32 0
# GFX10: V_CMP_EQ_F32
---
name: hazard_smem_war_in_bundle
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
BUNDLE implicit-def $sgpr0_sgpr1 {
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
}
S_ENDPGM 0
...
# GFX9-LABEL: name: hazard_ignore_dbg_label_in_bundle
# GFX9: DBG_LABEL 6
# GFX9-NEXT: S_NOP 0
# GFX9: S_SENDMSG 3, implicit $exec, implicit $m0
---
name: hazard_ignore_dbg_label_in_bundle
body: |
bb.0:
BUNDLE {
$m0 = S_MOV_B32 killed $sgpr12
DBG_LABEL 0
DBG_LABEL 1
DBG_LABEL 2
DBG_LABEL 3
DBG_LABEL 4
DBG_LABEL 5
DBG_LABEL 6
S_SENDMSG 3, implicit $exec, implicit $m0
}
S_ENDPGM 0
...
# GCN-LABEL: name: vmem_vcc_hazard_in_bundle
# GCN: S_LOAD_DWORDX2_IMM
# GFX9-NEXT: S_NOP 3
# GCN: BUFFER_LOAD_DWORD_OFFEN
---
name: vmem_vcc_hazard_in_bundle
body: |
bb.0:
BUNDLE {
$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
$vgpr0 = IMPLICIT_DEF
$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0
$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, implicit $exec
}
S_ENDPGM 0
...