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7f0d01b1a0
We have a single noret intrinsic an a lot of special handling around it. Declare it just as any other but do not define rtn instructions itself instead. Differential Revision: https://reviews.llvm.org/D87719
73 lines
3.7 KiB
LLVM
73 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 -amdgpu-atomic-optimizations=false -verify-machineinstrs < %s | FileCheck %s -check-prefix=CHECK
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define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
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; CHECK-LABEL: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_mov_b32 s11, s5
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; CHECK-NEXT: s_mov_b32 s10, s4
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; CHECK-NEXT: s_mov_b32 s9, s3
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; CHECK-NEXT: s_mov_b32 s8, s2
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; CHECK-NEXT: buffer_atomic_add_f32 v0, v1, s[8:11], s6 offen
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; CHECK-NEXT: s_endpgm
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%ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 24)
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ret void
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}
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define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
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; CHECK-LABEL: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_mov_b32 s11, s5
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; CHECK-NEXT: s_mov_b32 s10, s4
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; CHECK-NEXT: s_mov_b32 s9, s3
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; CHECK-NEXT: s_mov_b32 s8, s2
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; CHECK-NEXT: buffer_atomic_add_f32 v0, off, s[8:11], s6
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; CHECK-NEXT: s_endpgm
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%ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 0, i32 %soffset, i32 0)
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ret void
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}
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define amdgpu_ps void @raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
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; CHECK-LABEL: raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_mov_b32 s11, s5
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; CHECK-NEXT: s_mov_b32 s10, s4
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; CHECK-NEXT: s_mov_b32 s9, s3
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; CHECK-NEXT: s_mov_b32 s8, s2
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; CHECK-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[8:11], s6 offen
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; CHECK-NEXT: s_endpgm
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%ret = call <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
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ret void
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}
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define amdgpu_ps void @raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
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; CHECK-LABEL: raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_mov_b32 s11, s5
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; CHECK-NEXT: s_mov_b32 s10, s4
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; CHECK-NEXT: s_mov_b32 s9, s3
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; CHECK-NEXT: s_mov_b32 s8, s2
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; CHECK-NEXT: buffer_atomic_pk_add_f16 v0, off, s[8:11], s6 offset:92
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; CHECK-NEXT: s_endpgm
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%ret = call <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 92, i32 %soffset, i32 0)
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ret void
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}
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define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
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; CHECK-LABEL: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_mov_b32 s11, s5
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; CHECK-NEXT: s_mov_b32 s10, s4
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; CHECK-NEXT: s_mov_b32 s9, s3
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; CHECK-NEXT: s_mov_b32 s8, s2
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; CHECK-NEXT: buffer_atomic_add_f32 v0, v1, s[8:11], s6 offen slc
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; CHECK-NEXT: s_endpgm
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%ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2)
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ret void
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}
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declare float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i32 immarg) #0
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declare <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i32>, i32, i32, i32 immarg) #0
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attributes #0 = { nounwind }
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