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f1ba6f4d9b
gfx90a operations require even aligned registers, but this was previously achieved by reserving registers inside the full class. Ideally this would be captured in the static instruction definitions for the operands, and we would have different instructions per subtarget. The hackiest part of this is we need to manually reassign AGPR register classes after instruction selection (we get away without this for VGPRs since those types are actually registered for legal types).
95 lines
3.3 KiB
YAML
95 lines
3.3 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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# GCN-LABEL: name: ds_read_b32_v_v
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# GCN: vreg_64_align2 = DS_READ2_B32
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name: ds_read_b32_v_v
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body: |
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bb.0:
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%0:vgpr_32 = IMPLICIT_DEF
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%1:vgpr_32 = DS_READ_B32_gfx9 %0, 0, 0, implicit $exec :: (load 4 from `i32 addrspace(3)* undef`)
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%2:vgpr_32 = DS_READ_B32_gfx9 %0, 8, 0, implicit $exec :: (load 4 from `i32 addrspace(3)* undef`)
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...
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# GCN-LABEL: name: ds_read_b32_a_a
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# GCN: areg_64_align2 = DS_READ2_B32
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name: ds_read_b32_a_a
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body: |
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bb.0:
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%0:vgpr_32 = IMPLICIT_DEF
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%1:agpr_32 = DS_READ_B32_gfx9 %0, 0, 0, implicit $exec :: (load 4 from `i32 addrspace(3)* undef`)
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%2:agpr_32 = DS_READ_B32_gfx9 %0, 8, 0, implicit $exec :: (load 4 from `i32 addrspace(3)* undef`)
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...
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# GCN-LABEL: name: ds_read_b32_v_a
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# GCN: vgpr_32 = DS_READ_B32
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# GCN: agpr_32 = DS_READ_B32
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name: ds_read_b32_v_a
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body: |
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bb.0:
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%0:vgpr_32 = IMPLICIT_DEF
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%1:vgpr_32 = DS_READ_B32_gfx9 %0, 0, 0, implicit $exec :: (load 4 from `i32 addrspace(3)* undef`)
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%2:agpr_32 = DS_READ_B32_gfx9 %0, 8, 0, implicit $exec :: (load 4 from `i32 addrspace(3)* undef`)
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...
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# GCN-LABEL: name: ds_read_b32_a_v
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# GCN: agpr_32 = DS_READ_B32
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# GCN: vgpr_32 = DS_READ_B32
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name: ds_read_b32_a_v
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body: |
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bb.0:
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%0:vgpr_32 = IMPLICIT_DEF
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%1:agpr_32 = DS_READ_B32_gfx9 %0, 8, 0, implicit $exec :: (load 4 from `i32 addrspace(3)* undef`)
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%2:vgpr_32 = DS_READ_B32_gfx9 %0, 0, 0, implicit $exec :: (load 4 from `i32 addrspace(3)* undef`)
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...
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# GCN-LABEL: name: ds_write_b32_v_v
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# GCN: DS_WRITE2_B32_gfx9 %0, undef %1:vgpr_32, undef %2:vgpr_32
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name: ds_write_b32_v_v
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body: |
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bb.0:
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%0:vgpr_32 = IMPLICIT_DEF
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DS_WRITE_B32_gfx9 %0, undef %1:vgpr_32, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`)
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DS_WRITE_B32_gfx9 %0, undef %2:vgpr_32, 8, 0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`)
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...
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# GCN-LABEL: name: ds_write_b32_a_a
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# GCN: DS_WRITE_B32_gfx9 %0, undef %1:agpr_32
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# GCN: DS_WRITE_B32_gfx9 %0, undef %2:agpr_32
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name: ds_write_b32_a_a
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body: |
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bb.0:
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%0:vgpr_32 = IMPLICIT_DEF
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DS_WRITE_B32_gfx9 %0, undef %1:agpr_32, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`)
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DS_WRITE_B32_gfx9 %0, undef %2:agpr_32, 8, 0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`)
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...
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# GCN-LABEL: name: ds_write_b32_v_a
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# GCN: DS_WRITE_B32_gfx9 %0, undef %1:vgpr_32
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# GCN: DS_WRITE_B32_gfx9 %0, undef %2:agpr_32
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name: ds_write_b32_v_a
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body: |
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bb.0:
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%0:vgpr_32 = IMPLICIT_DEF
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DS_WRITE_B32_gfx9 %0, undef %1:vgpr_32, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`)
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DS_WRITE_B32_gfx9 %0, undef %2:agpr_32, 8, 0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`)
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...
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# GCN-LABEL: name: ds_write_b32_a_v
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# GCN: DS_WRITE_B32_gfx9 %0, undef %1:agpr_32
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# GCN: DS_WRITE_B32_gfx9 %0, undef %2:vgpr_32
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name: ds_write_b32_a_v
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body: |
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bb.0:
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%0:vgpr_32 = IMPLICIT_DEF
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DS_WRITE_B32_gfx9 %0, undef %1:agpr_32, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`)
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DS_WRITE_B32_gfx9 %0, undef %2:vgpr_32, 8, 0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`)
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...
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